Fairchild Semiconductor 100341SCX, 100341QIX, 100341QI, 100341QCX, 100341QC Datasheet

July 1988

Revised August 2000

100341

Low Power 8-Bit Shift Register

	General Description	Features
	The 100341 contains eight edge-triggered, D-type flip-flops	■ 35% power reduction of the 100141
	with individual inputs (Pn) and outputs (Qn) for parallel	■ 2000V ESD protection
	operation, and with serial inputs (Dn) and steering logic for	■ Pin/function compatible with 100141
	bidirectional shifting. The flip-flops accept input data a	■ Voltage compensated operating range = − 4.2V to − 5.7V
	setup time before the positive-going transition of the clock
		■ Available to industrial grade temperature range
	pulse and their outputs respond a propagation delay after
	this rising clock edge.

The circuit operating mode is determined by the Select inputs S0 and S1, which are internally decoded to select either “parallel entry”, “hold”, “shift left” or “shift right” as described in the Truth Table. All inputs have 50 kΩ pulldown resistors.

Ordering Code:

Order Number	Package Number	Package Description
10034SC	M24B	24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100341PC	N24E	24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100341QI	V28A	28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100341QC	V28A	28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
		Industrial Temperature Range (− 40° C to + 85° C)

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol	Connection Diagrams
	24-Pin DIP/SOIC

Pin Descriptions

Pin Names	Description	28-Pin PLCC
CP	Clock Input
S0, S1	Select Inputs
D0, D7	Serial Inputs
P0–P7	Parallel Inputs
Q0–Q7	Data Outputs

Register Shift Bit-8 Power Low 100341

© 2000 Fairchild Semiconductor Corporation

DS009880

www.fairchildsemi.com

100341

Truth Table

Function

Inputs

Outputs

D7

D0

S1

S0

CP Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

Load Register

X

X

L

L

P7

P6

P5

P4

P3

P2

P1

P0

Shift Left

X

L

L

H

Q6

Q5

Q4

Q3

Q2

Q1

Q0

L

Shift Left

X

H

L

H

Q6

Q5

Q4

Q3

Q2

Q1

Q0

H

Shift Right

L

X

H

L

L

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Shift Right

H

X

H

L

H

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Hold

X

X

H

H

X

Hold

X

X

X

X

H

No Change

Hold

X

X

X

X

L

H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

= LOW-to-HIGH Transition

Logic Diagram

www.fairchildsemi.com

2

Absolute Maximum Ratings(Note 1)

Storage Temperature (TSTG)	− 65° C to + 150° C
Maximum Junction Temperature (TJ)	+ 150° C
VEE Pin Potential to Ground Pin	− 7.0V to + 0.5V
Input Voltage (DC)	VEE to + 0.5V
Output Current (DC Output HIGH)	− 50 mA
ESD (Note 2)	≥ 2000V

Recommended Operating

Conditions

Case Temperature (TC)
Commercial	0° C to + 85° C
Industrial	− 40° C to + 85° C
Supply Voltage (VEE)	− 5.7V to − 4.2V

Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version
DC Electrical Characteristics				(Note 3)
VEE = − 4.2V to − 5.7V, VCC = VCCA =		GND, TC = 0° C to + 85° C
Symbol	Parameter		Min	Typ	Max	Units		Conditions
VOH	Output HIGH Voltage		− 1025	− 955	− 870	mV	VIN =	VIH (Max)	Loading with
VOL	Output LOW Voltage		− 1830	− 1705	− 1620	mV	or VIL (Min)		50Ω	to − 2.0V
VOHC	Output HIGH Voltage		− 1035			mV	VIN =	VIH (Min)	Loading with
VOLC	Output LOW Voltage				− 1610	mV	or VIL (Max)		50Ω	to − 2.0V
VIH	Input HIGH Voltage		− 1165		− 870	mV	Guaranteed HIGH Signal
							for all Inputs
VIL	Input LOW Voltage		− 1830		− 1475	mV	Guaranteed LOW Signal
							for all Inputs
IIL	Input LOW Current		0.50			µ A	VIN =	VIL (Min)
IIH	Input HIGH Current				240	µ A	VIN =	VIH (Max)
IEE	Power Supply Current						Inputs OPEN
			− 157		− 75	mA	VEE =	− 4.2V to − 4.8V
			− 167		− 75	mA	VEE =	− 4.2V to − 5.7V

Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.

DIP AC Electrical Characteristics

	VEE = − 4.2V to − 5.7V, VCC =		VCCA = GND
	Symbol	Parameter		TC = 0° C		TC = + 25° C		TC = + 85° C		Units	Conditions
				Min	Max	Min	Max	Min	Max
	fMAX	Max Clock Frequency		400		400		400		MHz	Figures 2, 3
	tPLH	Propagation Delay		0.90	1.90	1.00	2.00	1.00	2.10	ns	Figures 1, 3
	tPHL	CP to Output									(Note 4)
	tTLH	Transition Time		0.35	1.30	0.35	1.30	0.35	1.30	ns	Figures 1, 3
	tTHL	20% to 80%, 80% to 20%
	tS	Setup Time	Dn, Pn	0.65		0.65		0.65		ns
			Sn	1.60		1.60		1.60			Figure 4
	tH	Hold	Dn, Pn	0.80		0.80		0.80		ns
			Sn	0.60		0.60		0.60
	tPW(H)	Pulse Width HIGH	CP	2.00		2.00		2.00		ns	Figure 3

Note 4: The propagation delay specified is for the switching of a single output. Delays may vary up to 0.40 ns if multiple outputs are switching simultaneously.

100341

3	www.fairchildsemi.com