Fairchild Semiconductor 74ABT374CSJX, 74ABT374CSJ, 74ABT374CSCX, 74ABT374CSC, 74ABT374CPC Datasheet
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November 1992
Revised November 1999
74ABT374
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The ABT374 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops.
Features
■Edge-triggered D-type inputs
■Buffered positive edge-triggered clock
■3-STATE outputs for bus-oriented applications
■Output sink capability of 64 mA, source capability of 32 mA
■Guaranteed output skew
■Guaranteed multiple output switching specifications
■Output switching specified for both 50 pF and 250 pF loads
■Guaranteed simultaneous switching, noise level and dynamic threshold performance
■Guaranteed latchup protection
■High impedance glitch free bus loading during entire power up and power down cycle
■Non-destructive hot insertion capability
Ordering Code:
Order Number |
Package Number |
Package Description |
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74ABT374CSC |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body |
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74ABT374CSJ |
M20D |
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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74ABT374CMSA |
MSA20 |
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide |
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74ABT374CMTC |
MTC20 |
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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74ABT374CPC |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram |
Pin Descriptions |
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Pin Names |
Description |
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D0–D7 |
Data Inputs |
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CP |
Clock Pulse Input (Active Rising Edge) |
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3-STATE Output Enable Input (Active LOW) |
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OE |
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O0–O7 |
3-STATE Outputs |
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Outputs STATE-3 with Flop-Flip Type-D Octal 74ABT374
© 1999 Fairchild Semiconductor Corporation |
DS011510 |
www.fairchildsemi.com |
74ABT374
Functional Description
The ABT374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs are in a high impedance state. Operation of the OE input does not affect the state of the flipflops.
Logic Diagram
Function Table
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Inputs |
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Internal |
Outputs |
Function |
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OE |
CP |
D |
Q |
O |
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H |
H |
L |
NC |
Z |
Hold |
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H |
H |
H |
NC |
Z |
Hold |
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H |
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L |
L |
Z |
Load |
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H |
H |
H |
Z |
Load |
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L |
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L |
L |
L |
Data Available |
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L |
H |
H |
H |
Data Available |
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L |
H |
L |
NC |
NC |
No Change in Data |
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L |
H |
H |
NC |
NC |
No Change in Data |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Storage Temperature |
− 65° C to + 150° C |
Ambient Temperature under Bias |
− 55° C to + 125° C |
Junction Temperature under Bias |
− 55° C to + 150° C |
VCC Pin Potential to |
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Ground Pin |
− 0.5V to + 7.0V |
Input Voltage (Note 2) |
− 0.5V to + 7.0V |
Input Current (Note 2) |
− 30 mA to + 5.0 mA |
Voltage Applied to Any Output |
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in the Disabled or |
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Power-Off State |
− 0.5V to 5.5V |
in the HIGH State |
− 0.5V to VCC |
Current Applied to Output |
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in LOW State (Max) |
twice the rated IOL (mA) |
Recommended Operating
Conditions
Free Air Ambient Temperature |
− 40° C to + 85° C |
Supply Voltage |
+ 4.5V to + 5.5V |
Minimum Input Edge Rate (∆ V/∆ t) |
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Data Input |
50 mV/ns |
Enable Input |
20 mV/ns |
Clock Input |
100mV/ns |
DC Latchup Source Current: |
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− 150 mA |
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OE |
Pin |
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(Across Comm Operating Range) |
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Note 1: Absolute maximum ratings are values beyond which the device |
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Other Pins |
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− 500 mA |
may be |
damaged or have its useful life impaired. Functional operation |
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under these conditions is not implied. |
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Over Voltage Latchup (I/O) |
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10V Note 2: Either voltage limit or current limit is sufficient to protect inputs |
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DC Electrical Characteristics |
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Symbol |
Parameter |
Min |
Typ |
Max |
Units |
VCC |
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Conditions |
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VIH |
Input HIGH Voltage |
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2.0 |
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V |
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Recognized HIGH Signal |
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VIL |
Input LOW Voltage |
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0.8 |
V |
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Recognized LOW Signal |
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VCD |
Input Clamp Diode Voltage |
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− 1.2 |
V |
Min |
IIN = |
− 18 mA |
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VOH |
Output HIGH Voltage |
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2.5 |
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V |
Min |
IOH = |
− |
3 mA |
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2.0 |
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V |
Min |
IOH = |
− |
32 mA |
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VOL |
Output LOW Voltage |
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0.55 |
V |
Min |
IOL = |
64 mA |
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IIH |
Input HIGH Current |
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1 |
µ A |
Max |
VIN = |
2.7V (Note 4) |
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1 |
VIN = |
VCC |
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IBVI |
Input HIGH Current Breakdown Test |
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7 |
µ A |
Max |
VIN = |
7.0V |
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IIL |
Input LOW Current |
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− 1 |
µ A |
Max |
VIN = |
0.5V (Note 4) |
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− 1 |
VIN = |
0.0V |
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VID |
Input Leakage Test |
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4.75 |
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V |
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0.0 |
IID = |
1.9 µ A, All Other Pins Grounded |
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IOZH |
Output Leakage Current |
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10 |
µ A |
0 − |
5.5V |
VOUT = |
2.7V; |
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= |
2.0V |
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OE |
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IOZL |
Output Leakage Current |
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− 10 |
µ A |
0 − |
5.5V |
VOUT = |
0.5V; |
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= |
2.0V |
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OE |
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IOS |
Output Short-Circuit Current |
− 100 |
− 275 |
mA |
Max |
VOUT = |
0.0V |
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ICEX |
Output High Leakage Current |
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50 |
µ A |
Max |
VOUT = |
VCC |
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IZZ |
Bus Drainage Test |
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100 |
µ A |
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0.0 |
VOUT = |
5.5V; All Others VCC or GND |
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ICCH |
Power Supply Current |
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50 |
µ A |
Max |
All Outputs HIGH |
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ICCL |
Power Supply Current |
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30 |
mA |
Max |
All Outputs LOW |
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ICCZ |
Power Supply Current |
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50 |
µ A |
Max |
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= |
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OE |
VCC; All Others at VCC or GND |
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ICCT |
Additional ICC/Input |
Outputs Enabled |
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2.5 |
mA |
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VI = |
VCC − 2.1V |
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Outputs 3-STATE |
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2.5 |
mA |
Max |
Enable Input VI = VCC − 2.1V |
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Outputs 3-STATE |
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2.5 |
mA |
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Data Input VI = VCC − 2.1V |
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All Others at VCC or GND |
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ICCD |
Dynamic ICC |
No Load |
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mA/ |
Max |
Outputs OPEN |
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(Note 4) |
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0.30 |
MHz |
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GND, (Note 3) |
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OE |
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One Bit Toggling, 50% Duty Cycle |
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Note 3: For 8-bit toggling, ICCD < 0.8 mA/MHz.
Note 4: Guaranteed, but not tested.
74ABT374
3 |
www.fairchildsemi.com |
74ABT374
DC Electrical Characteristics
(SOIC package)
Symbol |
Parameter |
Min |
Typ |
Max |
Units |
VCC |
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Conditions |
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CL = 50 pF, RL = 500Ω |
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VOLP |
Quiet Output Maximum Dynamic VOL |
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0.5 |
0.8 |
V |
5.0 |
TA = |
25° C (Note 5) |
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VOLV |
Quiet Output Minimum Dynamic VOL |
− 1.3 |
− 0.9 |
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V |
5.0 |
TA = |
25° C (Note 5) |
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VOHV |
Minimum HIGH Level Dynamic Output Voltage |
2.5 |
3.0 |
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V |
5.0 |
TA = |
25° C (Note 6) |
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VIHD |
Minimum HIGH Level Dynamic Input Voltage |
2.0 |
1.6 |
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V |
5.0 |
TA = |
25° C (Note 7) |
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VILD |
Maximum LOW Level Dynamic Input Voltage |
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1.3 |
0.8 |
V |
5.0 |
TA = |
25° C (Note 7) |
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Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not tested.
Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 7: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP Package) |
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TA = + 25° C |
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TA = |
− |
55° C to |
TA = − 40° C to + 85° C |
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+ 125° C |
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Symbol |
Parameter |
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VCC = |
+ 5.0V |
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VCC = |
4.5V to 5.5V |
VCC = 4.5V to 5.5V |
Units |
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CL = |
50 pF |
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CL = |
50 pF |
CL = |
50 pF |
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Min |
Typ |
Max |
Min |
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Max |
Min |
Max |
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fMAX |
Maximum Clock Frequency |
150 |
200 |
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150 |
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150 |
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MHz |
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tPLH |
Propagation Delay |
2.0 |
3.2 |
5.0 |
1.4 |
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6.6 |
2.0 |
5.0 |
ns |
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tPHL |
CP to On |
2.0 |
3.3 |
5.0 |
2.0 |
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7.6 |
2.0 |
5.0 |
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tPZH |
Output Enable Time |
1.5 |
3.1 |
5.3 |
0.8 |
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5.7 |
1.5 |
5.3 |
ns |
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tPZL |
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1.5 |
3.1 |
5.3 |
1.5 |
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7.2 |
1.5 |
5.3 |
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tPHZ |
Output Disable Time |
1.5 |
3.6 |
5.4 |
1.3 |
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7.2 |
1.5 |
5.4 |
ns |
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tPLZ |
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1.5 |
3.4 |
5.4 |
1.0 |
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7.0 |
1.5 |
5.4 |
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AC Operating Requirements
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TA = |
+ 25° C |
TA = − 55° C to + 125° C |
TA = − 40° C to + 85° C |
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Symbol |
Parameter |
VCC = |
+ 5.0V |
VCC = |
4.5V to 5.5V |
VCC = |
4.5V to 5.5V |
Units |
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CL = |
50 pF |
CL = 50 pF |
CL = |
50 pF |
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Min |
Max |
Min |
Max |
Min |
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Max |
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tS(H) |
Setup Time, HIGH |
1.5 |
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2.5 |
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1.0 |
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ns |
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tS(L) |
or LOW Dn to CP |
1.5 |
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2.5 |
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1.5 |
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tH(H) |
Hold Time, HIGH |
1.0 |
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2.5 |
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1.0 |
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tH(L) |
or LOW Dn to CP |
1.0 |
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2.5 |
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1.0 |
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tW(H) |
Pulse Width, CP |
3.0 |
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3.3 |
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3.0 |
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ns |
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tW(L) |
HIGH or LOW |
3.0 |
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3.3 |
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3.0 |
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4 |
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