Fairchild Semiconductor 74ABT543CSPC, 74ABT543CSCX, 74ABT543CSC, 74ABT543CMTCX, 74ABT543CMTC Datasheet

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November 1992

Revised January 1999

74ABT543

Octal Registered Transceiver with 3-STATE Outputs

General Description

The ABT543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow.

Features

■Back-to-back registers for storage

■Bidirectional data path

■Separate controls for data flow in each direction

■Guaranteed output skew

■Guaranteed multiple output switching specifications

■Output switching specified for both 50 pF and 250 pF loads

■Guaranteed simultaneous switching noise level and dynamic threshold performance

■Guaranteed latchup protection

■High impedance glitch free bus loading during entire power up and power down cycle

■Nondestructive hot insertion capability

■A and B outputs have current sourcing capability of 32 mA and current sinking capability of 64 mA

Ordering Code:

Order Number	Package Number	Package Description

74ABT543CSC	M24B	24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

74ABT543CMSA	MSA24	24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

74ABT543CMTC	MTC24	24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Assignment for

Pin Names

Description

SOIC, SSOP and TSSOP

OEAB, OEBA

Output Enable Inputs

Latch Enable Inputs

LEAB,

LEBA

Chip Enable Inputs

CEAB,

CEBA

A0–A7

Side A Inputs or 3-STATE Outputs

B0–B7

Side B Inputs or 3-STATE Outputs

Outputs STATE-3 with Transceiver Registered Octal 74ABT543

DS011508.prf

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74ABT543

Functional Description

The ABT543 contains two sets of D-type latches, with separate input and output controls for each. For data flow from A to B, for example, the A to B Enable (CEAB) input must be low in order to enter data from the A Port or take data from the B Port as indicated in the Data I/O Control Table. With CEAB low, a low signal on (LEAB) input makes the A to B latches transparent; a subsequent low to high transition of the LEAB line puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both low, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using

the CEBA, LEBA and OEBA.

Logic Diagram

Data I/O Control Table

	Inputs			Latch Status	Output Buffers

CEAB		LEAB	OEAB

H		X	X	Latched	HIGH Z
X		H	X	Latched	—
L		L	X	Transparent	—
X		X	H	—	HIGH Z
L		X	L	—	Driving

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

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Absolute Maximum Ratings(Note 1)

Storage Temperature	−65°C to +150°C
Ambient Temperature under Bias	−55°C to +125°C
Junction Temperature under Bias	−55°C to +150°C
VCC Pin Potential to	−0.5V to +7.0V
Ground Pin	−0.5V to +7.0V
Input Voltage (Note 2)	−0.5V to +7.0V
Input Current (Note 2)	−30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disable or Power-Off State	−0.5V to +5.5V
in the HIGH State	−0.5V to VCC
Current Applied to Output
in LOW State (Max)	twice the rated IOL (mA)
	twice the rated IOL (mA)

DC Latchup Source Current	−500 mA
Over Voltage Latchup (I/O)	10V

Recommended Operating

Conditions

Free Air Ambient Temperature	−40°C to +85°C
Supply Voltage	+4.5V to +5.5V
Minimum Input Edge Rate ( V/	t)
Data Input	50 mV/ns
Enable Input	20 mV/ns
Clock Input	100 mV/ns

Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

DC Electrical Characteristics

Symbol

Parameter

Min

Typ

Max

Units

VCC

Conditions

VIH

Input HIGH Voltage

2.0

Recognized HIGH Signal

VIL

Input LOW Voltage

0.8

Recognized LOW Signal

VCD

Input Clamp Diode Voltage

−1.2

IIN = −18 mA (Non I/O Pins)

VOH

Output HIGH Voltage

2.5

IOH = −3 mA, (An, Bn)

2.0

IOH = −32 mA, (An, Bn)

VOL

Output LOW Voltage

0.55

Min

IOL = 64 mA, (An, Bn)

VID

Input Leakage Test

4.75

0.0

IID = 1.9 μA, (Non-I/O Pins)

All Other Pins Grounded

IIH

Input HIGH Current

μA

Max

VIN = 2.7V (Non-I/O Pins) (Note 3)

VIN = VCC (Non-I/O Pins)

IBVI

Input HIGH Current Breakdown Test

μA

Max

VIN = 7.0V (Non-I/O Pins)

IBVIT

Input HIGH Current

100

μA

Max

VIN = 5.5V (An, Bn)

Breakdown Test (I/O)

IIL

Input LOW Current

−1

μA

Max

VIN = 0.5V (Non-I/O Pins) (Note 3)

−1

VIN = 0.0V (Non-I/O Pins)

IIH + IOZH

Output Leakage Current

μA

0V–5.5V

VOUT = 2.7V (An, Bn);

= 2V

OEAB

CEAB

IIL + IOZL

Output Leakage Current

−10

μA

0V–5.5V

VOUT = 0.5V (An, Bn);

= 2V

OEAB

CEAB

IOS

Output Short-Circuit Current

−100

−275

Max

VOUT = 0V (An, Bn)

ICEX

Output HIGH Leakage Current

μA

Max

VOUT = VCC (An, Bn)

IZZ

Bus Drainage Test

100

μA

0.0V

VOUT = 5.5V (An, Bn);

All Others GND

ICCLH

Power Supply Current

μA

Max

All Outputs HIGH

ICCL

Power Supply Current

Max

All Outputs LOW

ICCZ

Power Supply Current

μA

Max

Outputs 3-STATE

All Others at VCC or GND

ICCT

Additional ICC/Input

2.5

Max

VI = VCC − 2.1V

All Others at VCC or GND

ICCD

Dynamic ICC

No Load

Outputs Open,

CEAB

(Note 5)

0.18

mA/MHz

Max

and

= GND,

= VCC, One Bit Toggling,

OEAB

CEBA

50% Duty Cycle, (Note 4)

Note 3: Guaranteed but not tested.

Note 4: For 8-bit toggling. ICCD < 1.4 mA/MHz.

Note 5: Guaranteed, but not tested.

74ABT543

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