Fairchild Semiconductor 74ABT16501CMTDX, 74ABT16501CMTD, 74ABT16501CCW, 74ABT16501CSSCX, 74ABT16501CSSC Datasheet
January 1995
Revised January 1999
74ABT16501
18-Bit Universal Bus Transceivers with 3-STATE Outputs
General Description
The ABT16501 18-bit universal bus transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. Output-enable OEAB is active-high. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active HIGH and OEBA is active LOW).
To ensure the high-impedance state during power up or power down, OE inputs should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Features
■Combines D-Type latches and D-Type flip-flops for operation in transparent, latched, or clocked mode
■Flow-through architecture optimizes PCB layout
■Guaranteed latch-up protection
■High impedance glitch free bus loading during entire power up and power down cycle
■Non-destructive hot insertion capability
Ordering Code:
Order Number |
Package Number |
Package Description |
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74ABT16501CSSC |
MS56A |
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide |
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74ABT16501CMTD |
MTD56 |
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide |
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Devices also available in Tape or Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignment for SSOP
Function Table (Note 1)
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Inputs |
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Output |
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B |
OEAB |
LEAB |
CLKAB |
A |
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L |
X |
X |
X |
Z |
H |
H |
X |
L |
L |
H |
H |
X |
H |
H |
H |
L |
− |
L |
L |
H |
L |
− |
H |
H |
H |
L |
H |
X |
B0 (Note 2) |
H |
L |
L |
X |
B0 (Note 3) |
Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA.
Note 2: Output level before the indicated steady-state input conditions were established.
Note 3: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
Outputs STATE-3 with Transceivers Bus Universal Bit-18 74ABT16501
© 1999 Fairchild Semiconductor Corporation |
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www.fairchildsemi.com |
74ABT16501
Logic Diagram
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2 |
Absolute Maximum Ratings(Note 4)
Storage Temperature |
−65°C to +150°C |
Ambient Temperature under Bias |
−55°C to +125°C |
Junction Temperature under Bias |
−55°C to +150°C |
VCC Pin Potential to |
−0.5V to +7.0V |
Ground Pin |
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Input Voltage (Note 5) |
−0.5V to +7.0V |
Input Current (Note 5) |
−30 mA to +5.0 mA |
Voltage Applied to Any Output |
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in the Disabled or |
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Power-off State |
−0.5V to 5.5V |
in the HIGH State |
−0.5V to VCC |
Current Applied to Output |
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in LOW State (Max) |
twice the rated IOL (mA) |
DC Latchup Source Current |
−500 mA |
Over Voltage Latchup (I/O) |
10V |
Recommended Operating
Conditions
Free Air Ambient Temperature |
−40°C to +85°C |
Supply Voltage |
+4.5V to +5.5V |
Minimum Input Edge Rate ( V/ |
t) |
Data Input |
50 mV/ns |
Enable Input |
20 mV/ns |
Note 4: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 5: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol |
Parameter |
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Min |
Typ |
Max |
Units |
VCC |
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Conditions |
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VIH |
Input HIGH Voltage |
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2.0 |
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V |
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Recognized HIGH Signal |
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VIL |
Input LOW Voltage |
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0.8 |
V |
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Recognized LOW Signal |
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VCD |
Input Clamp Diode Voltage |
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−1.2 |
V |
Min |
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IIN = −18 mA |
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VOH |
Output HIGH Voltage |
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2.5 |
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V |
Min |
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IOH = −3 mA |
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2.0 |
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V |
Min |
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IOH = −32 mA |
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VOL |
Output LOW Voltage |
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0.55 |
V |
Min |
IOL = 64 mA |
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IIH |
Input HIGH Current |
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1 |
μA |
Max |
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VIN = 2.7V (Note 6) |
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1 |
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VIN = VCC |
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IBVI |
Input HIGH Current Breakdown Test |
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7 |
μA |
Max |
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VIN = 7.0V |
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IIL |
Input LOW Current |
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−1 |
μA |
Max |
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VIN = 0.5V (Note 6) |
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−1 |
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VIN = 0.0V |
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VID |
Input Leakage Test |
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4.75 |
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V |
0.0 |
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IID = 1.9 μA |
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All Other Pins Grounded |
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IIH + |
Output Leakage Current |
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10 |
μA |
0 − 5.5V |
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VOUT = 2.7V; |
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OE = 2.0V |
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OE, |
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IOZH |
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IIL + |
Output Leakage Current |
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−10 |
μA |
0 − 5.5V |
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VOUT = 0.5V; |
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OE = 2.0V |
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OE, |
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IOZL |
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IOS |
Output Short-Circuit Current |
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−100 |
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−275 |
mA |
Max |
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VOUT = 0V |
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ICEX |
Output HIGH Leakage Current |
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50 |
μA |
Max |
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VOUT = VCC |
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IZZ |
Bus Drainage Test |
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100 |
μA |
0.0 |
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VOUT = 5.5V; All Others GND |
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ICCH |
Power Supply Current |
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1.0 |
mA |
Max |
All Outputs HIGH |
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ICCL |
Power Supply Current |
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68 |
mA |
Max |
An or Bn Outputs LOW |
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ICCZ |
Power Supply Current |
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1.0 |
mA |
Max |
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n = VCC, |
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OE |
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All Others at VCC or GND |
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ICCT |
Additional ICC/Input |
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2.5 |
mA |
Max |
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VI = VCC − 2.1V |
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All Others at VCC or GND |
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ICCD |
Dynamic ICC |
No Load |
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mA/ |
Max |
Outputs Open |
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(Note 6) |
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0.23 |
MHz |
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Transparent Mode |
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One Bit Toggling, 50% Duty Cycle |
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Note 6: Guaranteed, but not tested.
74ABT16501
3 |
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