Fairchild Semiconductor 100331SCX, 100331SC, 100331DC, 100331QIX, 100331QI Datasheet

February 1990

Revised August 2000

100331

Low Power Triple D-Type Flip-Flop

General Description

The 100331 contains three D-type, edge-triggered master/ slave flip-flops with true and complement outputs, a Common Clock (CPC), and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct Set (SDn) and Direct Clear (CDn) inputs. Data enters a master when both CPn and CPC are LOW and transfers to a slave when CPn or CPC (or both) go HIGH. The Master Set, Master Reset and individual CDn and SDn inputs override the Clock inputs. All inputs have 50 kΩ pull-down resistors.

Features

■35% power reduction of the 100131

■2000V ESD protection

■Pin/function compatible with 100131

■Voltage compensated operating range = − 4.2V to − 5.7V

■Available to industrial grade temperature range

Ordering Code:

Order Number	Package Number	Package Description
100331SC	M24B	24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100331PC	N24E	24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100331QC	V28A	28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100331QI	V28A	28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
		Industrial Temperature Range (− 40° C to + 85° C)

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol	Connection Diagrams
	24-Pin DIP/SOIC

Pin Descriptions

		Pin Names			Description	28-Pin PLCC
	CP0–CP2				Individual Clock Inputs
	CPC				Common Clock Input
	D0–D2				Data Inputs
	CD0–CD2				Individual Direct Clear Inputs
	SDn				Individual Direct Set Inputs
	MR				Master Reset Input
	MS				Master Set Input
	Q0-Q2				Data Outputs
	Q	0–Q		2	Complementary Data Outputs

Flop-Flip Type-D Triple Power Low 100331

© 2000 Fairchild Semiconductor Corporation

DS010262

www.fairchildsemi.com

100331

Truth Tables

Synchronous Operation (Each Flip-Flop)

			Inputs			Outputs
	Dn	CPn	CPC	MS	MR	Qn(t + 1)
				SDn	CDn
	L		L	L	L	L
	H		L	L	L	H
	L	L		L	L	L
	H	L		L	L	H
	X	L	L	L	L	Qn(t)
	X	H	X	L	L	Qn(t)
	X	X	H	L	L	Qn(t)

H =	HIGH Voltage Level
L =	LOW Voltage Level
X =	Don’t Care
U =	Undefined
t =	Time before CP Positive Transition
t + 1 =	Time after CP Positive Transition
=	LOW-to-HIGH Transition

Logic Diagram

Asynchronous Operation (Each Flip-Flop)

			Inputs			Outputs
	Dn	CPn	CPC	MS	MR	Qn(t + 1)
				SDn	CDn
	X	X	X	H	L	H
	X	X	X	L	H	L
	X	X	X	H	H	U

www.fairchildsemi.com

2

Absolute Maximum Ratings(Note 1)

Storage Temperature (TSTG)	− 65° C to + 150° C
Maximum Junction Temperature (TJ)	+ 150° C
Pin Potential to Ground Pin (VEE)	− 7.0V to + 0.5V
Input Voltage (DC)	VEE to + 0.5V
Output Current
(DC Output HIGH)	− 50 mA
ESD (Note 2)	≤ 2000V

Recommended Operating

Conditions

Case Temperature (TC)
Commercial	0° C to + 85° C
Industrial	− 40° C to + 85° C
Supply Voltage (VEE)	− 5.7V to − 4.2V

Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version

DC Electrical Characteristics (Note 3)

VEE = − 4.2V to − 5.7V, VCC = VCCA =		GND, TC =		0° C to + 85° C
Symbol	Parameter		Min	Typ	Max	Units		Conditions
VOH	Output HIGH Voltage		− 1025	− 955	− 870	mV	VIN =	VIH (Max)	Loading with
VOL	Output LOW Voltage		− 1830	− 1705	− 1620	mV	or VIL (Min)		50Ω to − 2.0V
VOHC	Output HIGH Voltage		− 1035			mV	VIN =	VIH (Min)	Loading with
VOLC	Output LOW Voltage				− 1610	mV	or VIL (Max)		50Ω to − 2.0V
VIH	Input HIGH Voltage		− 1165		− 870	mV	Guaranteed HIGH Signal
							for All Inputs
VIL	Input LOW Voltage		− 1830		− 1475	mV	Guaranteed LOW Signal
							for All Inputs
IIL	Input LOW Current		0.5			µ A	VIN =	VIL (Min)
IIH	Input HIGH Current				240	µ A	VIN =	VIH (Max)
IEE	Power Supply Current		− 122		− 65	mA	Inputs OPEN

Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.

100331

3	www.fairchildsemi.com