Fairchild Semiconductor 74ABT899CSCX, 74ABT899CSC, 74ABT899CQCX, 74ABT899CQC, 74ABT899CMSAX Datasheet

...

0 (0)

November 1992

Revised January 1999

74ABT899

9-Bit Latchable Transceiver with Parity Generator/Checker

General Description

The ABT899 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through transceiver or it can generate/check parity from the 8-bit data busses in either direction.

The ABT899 features independent latch enables for the A- to-B direction and the B-to-A direction, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity.

Features

■Latchable transceiver with output sink of 64 mA

■Option to select generate parity and check or “feed-through” data/parity in directions A-to-B or B-to-A

■Independent latch enables for A-to-B and B-to-A directions

■Select pin for ODD/EVEN parity

■ERRA and ERRB output pins for parity checking

■Ability to simultaneously generate and check parity

■May be used in systems applications in place of the 543 and 280

■May be used in system applications in place of the 657 and 373 (no need to change T/R to check parity)

■Guaranteed output skew

■Guaranteed multiple output switching specifications

■Output switching specified for both 50 pF and 250 pF loads

■Guaranteed simultaneous switching noise level and dynamic threshold performance

■Guaranteed latchup protection

■High impedance glitch free bus loading during entire power up and power down cycle

■Nondestructive hot insertion capability

■Disable time less than enable time to avoid bus contention

Ordering Code:

Order Number	Package Number	Package Description

74ABT899CSC	M28B	28-Lead Small Outline Integrated Circuit (SOIC), MS-013, 0.300” Wide Body

74ABT899CMSA	MSA28	28-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

74ABT899CQC	V28A	28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagrams	Pin Assignment for
	SOIC and SSOP
Pin Assignment
for PLCC

Generator/Checker Parity with Transceiver Latchable Bit-9 74ABT899

DS011509.prf

www.fairchildsemi.com

74ABT899

Pin Descriptions

Pin Names

Descriptions

A0–A7

A Bus Data Inputs/Data Outputs

B0–B7

B Bus Data Inputs/Data Outputs

APAR, BPAR

A and B Bus Parity Inputs/Outputs

ODD/EVEN

ODD/EVEN Parity Select,

Active LOW for EVEN Parity

Output Enables for A or B Bus,

GBA,

GAB

Active LOW

Select Pin for Feed-Through or

SEL

Generate Mode, LOW for Generate

Mode

LEA, LEB

Latch Enables for A and B Latches,

HIGH for Transparent Mode

Error Signals for Checking Generated

ERRA,

ERRB

Parity with Parity In, LOW if Error

Occurs

Functional Description

The ABT899 has three principal modes of operation which are outlined below. These modes apply to both the A-to-B and B-to-A directions.

•Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEB (LEA) is HIGH and the Mode Select (SEL) is LOW, the parity generated from B[0:7] (A[0:7]) can be checked and monitored by ERRB (ERRA).

•Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is HIGH. Parity is still generated and checked as ERRA and ERRB in the feed-through mode (can be used as an interrupt to signal a data/parity bit error to the CPU).

•Independent Latch Enables (LEA and LEB) allow other permutations of generating/checking (see Function Table below).

Function Table

Inputs

Operation

LEA

LEB

GAB

GBA

SEL

Busses A and B are 3-STATE.

Generates parity from B[0:7] based on O/E

(Note 1). Generated parity → APAR.

Generated parity checked against BPAR and output as ERRB.

Generated parity → APAR. Gener-

Generates parity from B[0:7] based on O/E.

ated parity checked against BPAR and output as ERRB. Generated parity also

fed back through the A latch for generate/check as ERRA.

Generated parity → APAR.

Generates parity from B latch data based on O/E.

Generated parity checked against latched BPAR and output as ERRB.

BPAR/B[0:7] → APAR/A0:7] Feed-through mode. Generated parity checked

against BPAR and output as ERRB.

BPAR/B[0:7] → APAR/A[0:7]

Feed-through mode. Generated parity checked against BPAR and output as

ERRB. Generated parity also fed back through the A latch for generate/check as

ERRA.

Generated parity → BPAR. Gener-

Generates parity for A[0:7] based on O/E.

ated parity checked against APAR and output as ERRA.

Generated parity → BPAR. Gener-

Generates parity from A[0:7] based on O/E.

ated parity checked against APAR and output as ERRA. Generated parity also

fed back through the B latch for generate/check as ERRB.

Generated parity → BPAR.

Generates parity from A latch data based on O/E.

Generated parity checked against latched APAR and output as ERRA.

APAR/A[0:7] → BPAR/B[0:7]

Feed-through mode. Generated parity checked against APAR and output as

ERRA.

APAR/A[0:7] → BPAR/B[0:7]

Feed-through mode. Generated parity checked against APAR and output as

ERRA. Generated parity also fed back through the B latch for generate/check as

ERRB.

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Note 1: O/E

= ODD/EVEN

www.fairchildsemi.com

Functional Block Diagram

74ABT899

3	www.fairchildsemi.com

74ABT899

Absolute Maximum Ratings(Note 2)

Storage Temperature	−65°C to +150°C
Ambient Temperature under Bias	−55°C to +125°C
Junction Temperature under Bias
Plastic	−55°C to +150°C
VCC Pin Potential to	−0.5V to +7.0V
Ground Pin	−0.5V to +7.0V
Input Voltage (Note 3)	−0.5V to +7.0V
Input Current (Note 3)	−30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disable or Power-
Off State	−0.5V to +5.5V
in the HIGH State	−0.5V to VCC
Current Applied to Output
in LOW State (Max)	twice the rated IOL (mA)
	twice the rated IOL (mA)

DC Latchup Source Current	−500 mA
Over Voltage Latchup (I/O)	10V

Recommended Operating

Conditions

Free Air Ambient Temperature	−40°C to +85°C
Supply Voltage	+4.5V to +5.5V
Minimum Input Edge Rate ( V/	t)
Data Input	50 mV/ns
Enable Input	20 mV/ns

Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.

Note 3: Either voltage limit or current limit is sufficient to protect inputs.

DC Electrical Characteristics

Symbol

Parameter

Min

Typ

Max

Units

VCC

Conditions

VIH

Input HIGH Voltage

2.0

Recognized HIGH Signal

VIL

Input LOW Voltage

0.8

Recognized LOW Signal

VCD

Input Clamp Diode Voltage

−1.2

Min

IIN = −18 mA (Non I/O Pins)

VOH

Output HIGH

2.5

Min

IOH = −3 mA, (An, Bn, APAR, BPAR)

Voltage

2.0

IOH = −32 mA, (An, Bn, APAR, BPAR)

VOL

Output LOW Voltage

0.55

Min

IOL = 64 mA, (An, Bn, APAR, BPAR)

VID

Input Leakage Test

4.75

0.0

IID = 1.9 μA, (Non-I/O Pins)

All Other Pins Grounded

IIH

Input HIGH Current

μA

Max

VIN = 2.7V (Non-I/O Pins) (Note 4)

VIN = VCC (Non-I/O Pins)

IBVI

Input HIGH Current

μA

Max

VIN = 7.0V (Non-I/O Pins)

Breakdown Test

IBVIT

Input HIGH Current

100

μA

Max

VIN = 5.5V (An, Bn, APAR, BPAR)

Breakdown Test (I/O)

IIL

Input LOW Current

−5

μA

Max

VIN = 0.5V (Non-I/O Pins) (Note 4)

VIN = 0.0V (Non-I/O Pins)

IIH + IOZH

Output Leakage Current

μA

0V–5.5V

VOUT = 2.7V (An, Bn);

and

= 2.0V

GAB

GBA

IIL + IOZL

Output Leakage Current

−50

μA

0V–5.5V

VOUT = 0.5V (An, Bn);

and

= 2.0V

GAB

GBA

IOS

Output Short-Circuit Current

−100

−275

Max

VOUT = 0V (An, Bn, APAR, BPAR)

ICEX

Output HIGH Leakage Current

μA

Max

VOUT = VCC (An, Bn, APAR, BPAR)

IZZ

Bus Drainage Test

100

μA

0.0V

VOUT = 5.5V (An, Bn, APAR, BPAR);

All Others GND

ICCH

Power Supply Current

250

μA

Max

All Outputs HIGH

ICCL

Power Supply Current

Max

All Outputs LOW, ERRA/B = HIGH (Note 5)

ICCZ

Power Supply Current

250

μA

Max

Outputs 3-STATE All Others at VCC or GND

ICCT

Additional ICC/Input

2.5

Max

VI = VCC − 2.1V All Others at VCC or GND

ICCD

Dynamic ICC: No Load

0.4

mA/MHz

Max

Outputs Open

(Note 4)

= GND, LE = HIGH

GAB

GBA

Non-I/O = GND or VCC

One bit toggling, 50% duty cycle

Note 4: Guaranteed, but not tested.

Note 5: Add 3.75 mA for each ERR LOW.

www.fairchildsemi.com

DC Electrical Characteristics

(PLCC package)

Symbol	Parameter	Min	Typ	Max	Units	VCC	Conditions
Symbol	Parameter	Min	Typ	Max	Units	VCC	CL = 50 pF, RL = 500Ω

VOLP	Quiet Output Maximum Dynamic VOL		0.8	1.1	V	5.0	TA = 25°C (Note 6)
VOLV	Quiet Output Minimum Dynamic VOL	−1.3	−0.8		V	5.0	TA = 25°C (Note 6)
VOHV	Minimum HIGH Level Dynamic Output Voltage	2.5	3.0		V	5.0	TA = 25°C (Note 8)
VIHD	Minimum HIGH Level Dynamic Input Voltage	2.2	1.8		V	5.0	TA = 25°C (Note 7)
VILD	Maximum LOW Level Dynamic Input Voltage		0.8	0.5	V	5.0	TA = 25°C (Note 7)

Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.

Note 7: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested.

Note 8: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.

AC Electrical Characteristics

(SOIC and PLCC Package)
															TA = +25°C		TA = −40°C to +85°C
Symbol									Parameter						VCC = +5.0V		VCC = 4.5V–5.5V		Units
Symbol									Parameter						CL = 50 pF		CL = 50 pF		Units
															CL = 50 pF		CL = 50 pF

														Min	Typ	Max	Min	Max

tPLH	Propagation Delay													1.5	3.0	4.8	1.5	4.8	ns
tPHL	An, to Bn													1.5	3.5	4.8	1.5	4.8
tPLH	Propagation Delay													2.5	5.9	9.2	2.5	9.2	ns
tPHL	An, Bn to BPAR, APAR													2.5	5.8	9.2	2.5	9.2
tPLH	Propagation Delay													2.5	5.4	8.5	2.5	8.5	ns
tPHL	An, Bn to													2.5	5.4	8.5	2.5	8.5
tPHL	An, Bn to			ERRA,						ERRB				2.5	5.4	8.5	2.5	8.5
tPLH	Propagation Delay													1.5	3.7	6.0	1.5	6.0	ns
tPHL	APAR, BPAR to													1.5	3.7	6.0	1.5	6.0
tPHL	APAR, BPAR to								ERRA,				ERRB	1.5	3.7	6.0	1.5	6.0
tPLH	Propagation Delay													2.0	4.4	6.9	2.0	6.9	ns
tPHL	ODD/EVEN to APAR, BPAR													2.0	4.4	6.9	2.0	6.9
tPLH	Propagation Delay													1.8	4.0	6.0	1.8	6.0	ns
tPHL					to									1.8	4.0	6.0	1.8	6.0
tPHL	ODD/EVEN				to			ERRA,				ERRB		1.8	4.0	6.0	1.8	6.0
tPLH	Propagation Delay													1.5	3.8	6.0	1.5	6.0	ns
tPHL	SEL to APAR, BPAR													1.5	3.8	6.0	1.5	6.0
tPLH	Propagation Delay													1.5	3.2	4.6	1.5	4.6	ns
tPHL	LEA, LEB to Bn, An													1.5	3.2	4.6	1.5	4.6
tPLH	Propagation Delay													2.5	5.9	8.8	2.5	8.8
tPHL	LEA, LEB to BPAR, APAR													2.5	5.7	8.8	2.5	8.8	ns
	Generate Mode

tPLH	Propagation Delay													1.5	3.6	5.1	1.5	5.1	ns
tPHL	LEA, LEB to BPAR, APAR,													1.5	3.6	5.1	1.5	5.1
	Feed Thru Mode

tPLH	Propagation Delay													1.6	5.4	8.4	1.6	8.4	ns
tPHL	LEA, LEB to													1.6	5.4	8.4	1.6	8.4
tPHL	LEA, LEB to						ERRA,				ERRB			1.6	5.4	8.4	1.6	8.4
tPZH	Output Enable Time													1.5	3.6	6.0	1.5	6.0	ns
tPZL		or				to An,								1.5	3.4	6.0	1.5	6.0
tPZL	GBA	or	GAB			to An,								1.5	3.4	6.0	1.5	6.0
	APAR or Bn, BPAR
tPHZ	Output Disable Time													1.0	4.0	6.0	1.0	6.0	ns
tPLZ		or				to A ,								1.0	3.3	6.0	1.0	6.0
tPLZ	GBA	or	GAB			to A ,								1.0	3.3	6.0	1.0	6.0
										n
	APAR or Bn, BPAR
tPLHtPHL	Propagation Delay													1.5	3.3	5.4	1.5	5.4	ns
	APAR to BPAR, BPAR to APAR													1.5	3.8	5.4	1.5	5.4

74ABT899

5	www.fairchildsemi.com

+ 11 hidden pages