Analog Devices AD6600ST-PCB, AD6600AST Datasheet

a		Dual Channel, Gain-Ranging
		ADC with RSSI
		AD6600

FEATURES

Dual IF Inputs, 70 MHz–250 MHz

Diversity or Two Independent IF Signals

Separate Attenuation Paths

Oversample RF Channels

20 MSPS on a Single Carrier

10 MSPS/Channel in Diversity Mode

Total Signal Range 90+ dB

30 dB from Automatic Gain-Ranging (AGC)

60 dB from A/D Converter

Range >100 dB After Processing Gain

Digital Outputs

11-Bit ADC Word

3-Bit RSSI Word

2 Clock, A/B Indicator

Single 5 V Power Supply

Output DVCC 3.3 V or 5 V

775 mW Power Dissipation

APPLICATIONS

Communications Receivers

PCS/Cellular Base Stations

GSM, CDMA, TDMA

Wireless Local Loop, Fixed Access

two input channels, each with 1 GHz input amplifiers and 30 dB of automatic gain-ranging circuitry. Both channels are sampled with a 450 MHz track-and-hold followed by an 11-bit, 20 MSPS analog-to-digital converter. Digital RSSI outputs, an A/B channel indicator, a 2× Clock output, references, and control circuitry are all on-chip. Digital output signals are two’s complement, CMOS-compatible and interface directly to 3.3 V or 5 V digital processing chips.

The primary use for the dual analog input structure is sampling both antennas in a two-antenna diversity receiver. However, Channels A and B may also be used to sample two independent IF signals. Diversity, or dual-channel mode, is limited to 10 MSPS per channel. In single-channel mode, the full clock rate of

20 MSPS may be applied to a single carrier.

The AD6600 may be used as a stand-alone sampling chip, or it may be combined with the AD6620 Digital Receive Signal Processor. The AD6620 provides 10 dB–25 dB of additional processing gain before passing data to a fixedor floating-point DSP.

Driving the AD6600 is simplified by using the AD6630 differential IF amplifier. The AD6630 is easily matched to inexpensive SAW filters from 70 MHz to 250 MHz.

Designed specifically for cellular/PCS receivers, the AD6600 supports GSM, IS-136, CDMA and Wireless LANs, as well as proprietary air interfaces used in WLL/fixed-access systems.

PRODUCT DESCRIPTION

The AD6600 mixed-signal receiver chip directly samples signals at analog input frequencies up to 250 MHz. The device includes

Units are available in plastic, surface-mount packages (44-lead LQFP) and specified over the industrial temperature range (–40°C to +85°C).

FUNCTIONAL BLOCK DIAGRAM

NOISE FILTER

				FLT		FLT
0dB, –12dB, –24dB					630	RESONANT
						PORT
AIN	ATTEN
AIN									AB_OUT
		GAIN	MUX	+12, +18dB	ENCODE			TWO'S
						A/D		COMPLEMENT
DETECT	SET	3	ANALOG	GAIN					D10–D0
						CONVERTER		11
PEAK	RSSI	RSSI
		GAIN						3	RSSI [2:0]
				SELECT GAIN
						ENCODE		RSSI
BIN
	ATTEN
BIN
						TIMING			CLK2
				AD6600
0dB, –12dB, –24dB
A_SEL		B_SEL		AVCC	GND	ENC	ENC	DVCC

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: [phone]	World Wide Web Site: http://www.analog.com
Fax: [phone]	© Analog Devices, Inc., 2000

AD6600–SPECIFICATIONS

DC SPECIFICATIONS (AVCC = 5 V, DVCC = 3.3 V; TMIN = –40 C, TMAX = +85 C unless otherwise noted.)

		Test		AD6600AST
Parameter	Temp	Level	Min	Typ	Max	Unit
ANALOG INPUTS (AIN, AIN/BIN, BIN)
Differential Analog Input Voltage Range1	Full	V		2.0		V p-p
Differential Analog Input Resistance2	Full	IV	160	200	240	Ω
Differential Analog Input Capacitance	25°C	V		1.5		pF
PEAK DETECTOR (Internal), RSSI
Resolution				3		Bits
RSSI Gain Step	Full	V		6		dB
RSSI Hysteresis3	Full	V		6		dB
RESONANT PORT (FLT, FLT)						Ω
Differential Port Resistance	Full	V		630
Differential Port Capacitance	Full	V		1.75		pF
A/D CONVERTER
Resolution	Full	IV		11		Bits
ENCODE INPUTS (ENC, ENC)
Differential Input Voltage (AC-Coupled)4	Full	IV	0.4			V p-p
Differential Input Resistance	25°C	V		11		kΩ
Differential Input Capacitance	25°C	V		2.5		pF
A/B MODE INPUTS (A_SEL, B_SEL)5
Input High Voltage Range	Full	IV	4.75		5.25	V
Input Low Voltage Range	Full	IV	0.0		0.5	V
POWER SUPPLY
Supply Voltages
AVCC	Full	II	4.75	5.0	5.25	V
DVCC	Full	IV	3.0	3.3	5.25	V
Supply Current
IAVCC (AVCC = 5.0 V)	Full	II		145	182	mA
IDVCC (DVCC = 3.3 V)	Full	II		15	20	mA
POWER CONSUMPTION6	Full	II		775	976	mW

NOTES

1Analog Input Range is a function of input frequency. See ac specifications for 70 MHz–250 MHz inputs. 2Analog Input Impedance is a function of input frequency. See ac specifications for 70 MHz–450 MHz inputs.

3Six dB of digital hysteresis is used to eliminate level uncertainty at the RSSI threshold points due to noise and amplitude variations. 4Encode inputs should be ac-coupled and driven differentially. See Encoding the AD6600 for details.

5A_SEL and B_SEL should be tied directly to ground or AVCC.

6Maximum power consumption is computed as maximum current at nominal supplies.

Specifications subject to change without notice.

DIGITAL SPECIFICATIONS (AVCC = 5 V, DVCC = 3.3 V; TMIN = –40 C, TMAX = +85 C unless otherwise noted.)

				Test		AD6600AST
Parameter			Temp	Level	Min	Typ	Max	Unit
LOGIC OUTPUTS (D10–D0, AB_OUT, RSSI2–0)1
Logic Compatibility						CMOS
Logic “1” Voltage (DVCC = 3.3 V)			Full	II	2.8	DVCC – 0.2		V
Logic “0” Voltage (DVCC = 3.3 V)			Full	II		0.2	0.5	V
Logic “1” Voltage (DVCC = 5.0 V)			Full	IV	4.0	DVCC – 0.35		V
Logic “0” Voltage (DVCC = 5.0 V)			Full	IV		0.35	0.5	V
Output Coding (D10–D0)						Two’s Complement
CLK2× OUTPUT1, 2
Logic “1” Voltage (DVCC = 3.3 V)			Full	II	2.8	DVCC – 0.2		V
Logic “0” Voltage (DVCC = 3.3 V)			Full	II		0.2	0.5	V
Logic “1” Voltage (DVCC = 5.0 V)			Full	IV	4.0	DVCC – 0.3		V
Logic “0” Voltage (DVCC = 5.0 V)			Full	IV		0.35	0.5	V

NOTES

1Digital output load is one LCX gate.

2CLK2× output voltage levels, high and low, tested at switching rate of 10 MHz.

Specifications subject to change without notice.

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TIMING REQUIREMENTS AND SWITCHING SPECIFICATIONS1							AD6600
(AVCC = 5 V, DVCC = 3.3 V; ENC and ENC = 20 MSPS; TMIN = –40 C, TMAX = +85 C unless otherwise noted.)
			Test		AD6600AST
Parameter	Name	Temp	Level	Min	Typ	Max	Unit
A/D CONVERTER
Conversion Rate	fENC				1/(tENC)		MSPS
Maximum Conversion Rate		Full	II	20			MSPS
Minimum Conversion Rate		Full	IV			6	MSPS
Aperture Uncertainty	tj	25°C	V		0.3		ps rms
ENCODE INPUTS (ENC, ENC)2
Period	tENC	Full	II	50			ns
Pulsewidth High3	tENCH	Full	IV	20			ns
Pulsewidth Low4	tENCL	Full	IV	20			ns
2× CLOCK OUTPUT (CLK2×)5					2× fENC
Output Frequency							MSPS
Output Period6	tCLK2×_1	Full	V		tENCL		ns
CLK2× Pulsewidth Low6	tCLK2×_2	Full	V		tENCH		ns
	tCLK2×L	Full	V		tENCH/2		ns
Output Risetime7		Full	V		3		ns
Output Falltime7		Full	V		2.6		ns
OUTPUT RISE/FALL TIMES8
Output Risetime (D10:D0, RSSI2:0)		Full	V		8		ns
Output Falltime (D10:D0, RSSI2:0)		Full	V		8.4		ns
Output Risetime (AB_OUT)		Full	V		6		ns
Output Falltime (AB_OUT)		Full	V		6.2		ns

NOTES

1See AD6600 Timing Diagrams.

2All switching specifications tested by driving ENC and ENC differentially.

3Several timing specifications are a function of Encode high time, tENCH; these specifications are shown in the data tables and timing diagrams. Encode duty cycle should be kept as close to 50% as possible.

4Encode pulse low directly affects the amount of settling time available at FLT resonant port. See External Analog (Resonant) Filter section for details.

5The 2× Clock is generated internally, therefore some specifications are functions of encode period and duty cycle. All timing measurements to or from CLK2 × are referenced to 2.0 V crossing.

6This specification IS a function of Encode period and duty cycle; reference timing diagrams Figure 8.

7Output rise time is measured from 20% point to 80% point of total CLK2× voltage swing; output fall time is measured from 80% point to 20% point of total CLK2 × voltage swing.

8Output rise time is measured from 20% point to 80% point of total data voltage swing; output fall time is measured from 80% point to 20% point of total data voltage swing. All outputs specified with 10 pF load.

Specifications subject to change without notice.

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AD6600–SPECIFICATIONS

TIMING REQUIREMENTS AND SWITCHING SPECIFICATIONS1, 2

(AVCC = 5 V, DVCC = 3.3 V; ENC and ENC = 20 MSPS, Duty Cycle = 50%; TMIN = –40 C, TMAX = +85 C unless otherwise noted.)

				Test		AD6600AST
Parameter		Name	Temp	Level	Min	Typ	Max	Unit
ENCODE/CLK2×
Encode Rising to CLK2× Falling3		tCF	Full	IV	6.5	8.0	9.5	ns
Encode Rising to CLK2× Rising4		tCR	Full	IV		tCF + (tENCH)/2		ns
@ Encode = 13	MSPS, 50% Duty Cycle		Full	IV	25.7	27.2	28.7	ns
@ Encode = 20	MSPS, 50% Duty Cycle		Full	IV	19.0	20.5	22.0	ns
CLK2×/DATA (D10:0, RSSI2:0)5
CLK2× to DATA Rising Low Delay3		t2×_DRL	Full	IV	3.0	6.5		ns
CLK2× to DATA Hold Time3		tH_D2×	Full	IV	3.0	6.5		ns
CLK2× to DATA Falling Low3, 6		t2×_DFL	25°C	IV	10.0	15.0	20.0	ns
CLK2× to DATA Setup Time4			Full	IV	11.0	15.5	22.0	ns
		tS_D2×	Full	IV		tENCH – t2×_DFL		ns
@ Encode = 13 MSPS, 50% Duty Cycle			Full	IV	16.5	23.0		ns
@ Encode = 20 MSPS, 50% Duty Cycle6			25°C	IV	5.0	10.0		ns
			Full	IV	3.0	9.5		ns
CLK2×/AB_OUT5
CLK2× to AB_OUT Rising Low Delay3		t2×_ARL	Full	IV	7.0	11.0		ns
CLK2× to AB_OUT Hold Time3		tH_A2×	Full	IV	7.0	11.0		ns
CLK2× to AB_OUT Falling Low Delay3, 6		t2×_AFL	25°C	IV	12.0	18.0	23.0	ns
CLK2× to AB_OUT Setup Time4			Full	IV	10.7	19.0	26.0	ns
		tS_A2×	Full	IV		tENCH – t2×_AFL		ns
@ Encode = 13 MSPS, 50% Duty Cycle			Full	IV	12.5	19.5		ns
@ Encode = 20 MSPS, 50% Duty Cycle6			25°C	IV	2.0	7.0		ns
			Full	IV	–1.0	6.0		ns
ENCODE/DATA (D10:0, RSSI2:0)
ENCODE to DATA Rising Low Delay4		tEN_DRL	Full	IV		tCR + t2×_DRL		ns
ENCODE to DATA Hold Time4		tH_DEN	Full	IV		tEN_DRL		ns
@ Encode = 13 MSPS, 50% Duty Cycle			Full	IV	28.7	33.7		ns
@ Encode = 20 MSPS, 50% Duty Cycle			Full	IV	22.0	27.0		ns
ENCODE to DATA Falling Low Delay4		tEN_DFL	Full	IV		tCR + t2×_DFL		ns
ENCODE to DATA Delay (Setup)4		tS_DEN	Full	IV		tENC – tEN_DFL		ns
@ Encode = 13 MSPS, 50% Duty Cycle			Full	IV	26.2	34.2		ns
@ Encode = 20 MSPS, 50% Duty Cycle6			25°C	IV	8.0	14.5		ns
			Full	IV	6.0	14.0		ns
ENCODE/AB_OUT
ENCODE to AB_OUT Rising Low Delay4		tEN_ARL	Full	IV		tCR + t2×_ARL		ns
ENCODE to AB_OUT Delay (Hold)4		tH_AEN	Full	IV		tEN_ARL		ns
@ Encode = 13 MSPS, 50% Duty Cycle			Full	IV	32.7	38.2		ns
@ Encode = 20 MSPS, 50% Duty Cycle			Full	IV	26.0	31.5		ns
ENCODE to AB_OUT Falling Low Delay4		tEN_AFL	Full	IV		tCR + t2×_AFL		ns
ENCODE to AB_OUT Delay (Setup)4		tS_AEN	Full	IV		tENC – tEN_AFL		ns
@ Encode = 13 MSPS, 50% Duty Cycle			Full	IV	22.2	30.7		ns
@ Encode = 20 MSPS, 50% Duty Cycle6			25°C	IV	5.0	11.5		ns
			Full	IV	2.0	10.5		ns

NOTES

1See AD6600 Timing Diagrams.

2All switching specifications tested by driving ENC and ENC differentially.

3This specification IS NOT a function of Encode period and duty cycle.

4This specification IS a function of Encode period and duty cycle.

5CLK2× referenced to 2.0 V crossing; digital output levels referenced to 0.8 V and 2.0 V crossings; all outputs with 10 pF load.

6For these particular specifications, the 25°C specification is valid from 25°C to 85°C. The Full temperature specification includes cold temperature extreme and covers the entire range, –40°C to +85°C.

Specifications subject to change without notice.

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AD6600

(AVCC = 5 V, DVCC = 3.3 V; ENC and ENC = 20 MSPS, Duty Cycle = 50%; TMIN = –40 C, TMAX = +85 C unless

AC SPECIFICATIONS otherwise noted.)

			Test		AD6600AST
Parameter		Temp	Level	Min	Typ	Max	Unit
ANALOG INPUTS1
Analog Input 3 dB Bandwidth2		Full	V		450		MHz
Differential Analog Input Voltage Range
70 MHz		Full	V		2.45		V p-p
150	MHz	Full	V		2.57		V p-p
200	MHz	Full	V		2.62		V p-p
250	MHz	Full	V		2.86		V p-p
Differential Analog Input Impedance3		25°C					Ω
70 MHz			V		197–j24
150	MHz	25°C	V		188–j48		Ω
200	MHz	25°C	V		175–j57		Ω
250	MHz	25°C	V		161–j67		Ω
300	MHz	25°C	V		151–j73		Ω
350	MHz	25°C	V		140–j80		Ω
400	MHz	25°C	V		141–j75		Ω
450	MHz	25°C	V		173–j107		Ω
Full-Scale Input Power
70 MHz		Full	V		5.8		dBm
150	MHz	Full	V		6.3		dBm
200	MHz	Full	V		6.7		dBm
250	MHz	Full	V		7.7		dBm
Full-Scale Gain Tolerance4					± 0.5
70 MHz–250 MHz		Full	V				dB
200	MHz5	25°C	I	–1.0	± 0.1	+1.0	dB
Gain Error
AIN = 200 MHz		25°C
@ –76 dBFS			I	–1.5		+1.5	dB
Gain Matching (Input A:B)					± 0.1
70 MHz–250 MHz		Full	V				dB
200	MHz	Full	II	–0.5	± 0.05	+0.5	dB
Range-to-Range Gain Tolerance					± 0.1
70 MHz–250 MHz		Full	V				dB
Range-to-Range Phase Tolerance
70 MHz		Full	V		0.2		Degree
250	MHz	Full	V		0.5		Degree
Channel Isolation6
70 MHz–250 MHz		Full	IV	45	50		dB
Noise7							µV rms
Minimum Attenuation Level		Full	V		34
Maximum Attenuation Level		Full	V		869		µV rms
Attenuator 3OIP8		Full	V		+33		dBm
Signal-to-Noise Ratio (SNR)9, 10, 11
AIN = 70 MHz		25°C
@ –1 dBFS			IV	55	59		dB
@ –6 dBFS		25°C	V		54.5		dB
@ –10 dBFS		25°C	IV	45	49		dB
@ –12 dBFS to –42 dBFS		25°C	IV	41	48 ± 6		dB
@ –54 dBFS		25°C	IV	31	34		dB
AIN = 150 MHz		25°C
@ –1 dBFS			IV	55	58		dB
@ –6 dBFS		25°C	V		54		dB
@ –10 dBFS		25°C	IV	45	49		dB
@ –12 dBFS to –42 dBFS		25°C	IV	41	48 ± 6		dB
@ –54 dBFS		25°C	IV	31	34		dB

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AD6600–SPECIFICATIONS

AC SPECIFICATIONS (continued)

		Test		AD6600AST
Parameter	Temp	Level	Min	Typ	Max	Unit
ANALOG INPUTS (Continued)
Signal-to-Noise Ratio (Continued)
AIN = 200 MHz	25°C
@ –1 dBFS		I	55	57.5		dB
@ –6 dBFS	25°C	V		53.5		dB
@ –10 dBFS	25°C	I	45	49		dB
@ –12 dBFS to –42 dBFS	25°C	I	40.5	48 ±6		dB
@ –54 dBFS	25°C	I	31	34		dB
AIN = 250 MHz	25°C
@ –1 dBFS		IV	52	56		dB
@ –6 dBFS	25°C	V		53.5		dB
@ –10 dBFS	25°C	IV	43	49		dB
@ –12 dBFS to –42 dBFS	25°C	IV	40	48 ±6		dB
@ –54 dBFS	25°C	IV	30	34		dB
SECOND HARMONIC
AIN = 70 MHz
@ –1 dBFS	Full	V		69		dBc
@ –6 dBFS	Full	V		68		dBc
@ –12 dBFS to –42 dBFS	Full	V		68 ±6		dBc
AIN = 150 MHz
@ –1 dBFS	Full	V		60		dBc
@ –6 dBFS	Full	V		59		dBc
@ –12 dBFS to –42 dBFS	Full	V		67 ±6		dBc
AIN = 200 MHz9, 10, 11	25°C
@ –1 dBFS		I	50	60		dBc
@ –6 dBFS	Full	V		56		dBc
@ –10 dBFS	25°C	I	48	55		dBc
@ –12 dBFS to –42 dBFS	Full	V		65 ±6		dBc
@ –54 dBFS	Full	V		50		dBc
AIN = 250 MHz
@ –1 dBFS	Full	V		54		dBc
@ –6 dBFS	Full	V		62		dBc
@ –12 dBFS to –42 dBFS	Full	V		65 ±6		dBc
THIRD HARMONIC
AIN = 70 MHz
@ –1 dBFS	Full	V		77		dBc
@ –6 dBFS	Full	V		76		dBc
@ –12 dBFS to –42 dBFS	Full	V		67 ±6		dBc
AIN = 150 MHz
@ –1 dBFS	Full	V		65		dBc
@ –6 dBFS	Full	V		70		dBc
@ –12 dBFS to –42 dBFS	Full	V		66 ±6		dBc
AIN = 200 MHz9, 10, 11	25°C
@ –1 dBFS		I	50	55		dBc
@ –6 dBFS	Full	V		58		dBc
@ –10 dBFS	25°C	I	55	66		dBc
@ –12 dBFS to –42 dBFS	Full	V		65 ±6		dBc
@ –54 dBFS	Full	V		62		dBc
AIN = 250 MHz
@ –1 dBFS	Full	V		50		dBc
@ –6 dBFS	Full	V		56		dBc
@ –12 dBFS to –42 dBFS	Full	V		65 ±6		dBc
AIN = 70 MHz–250 MHz
@ –75 dBFS	Full	IV	28	35		dBc

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							AD6600
AC SPECIFICATIONS (continued)
			Test		AD6600AST
Parameter		Temp	Level	Min	Typ	Max	Unit
WORST OTHER SPUR (4th or Higher)
AIN = 70 MHz
@ –1 dBFS		Full	V		74.5		dBc
@ –6 dBFS		Full	V		71		dBc
@ –12 dBFS to –42 dBFS		Full	V		68 ±6		dBc
AIN = 150 MHz
@ –1 dBFS		Full	V		67		dBc
@ –6 dBFS		Full	V		65		dBc
@ –12 dBFS to –42 dBFS		Full	V		67 ±6		dBc
AIN = 200 MHz		25°C
@ –1 dBFS			I	60	67		dBc
@ –6 dBFS		Full	V		66		dBc
@ –10 dBFS		25°C	I	55	66		dBc
@ –12 dBFS to –42 dBFS		Full	V		65 ±6		dBc
AIN = 250 MHz
@ –1 dBFS		Full	V		66.5		dBc
@ –6 dBFS		Full	V		65		dBc
@ –12 dBFS to –42 dBFS		Full	V		65 ±6		dBc

NOTES

1AIN, AIN/BIN, BIN: The AD6600 analog inputs are unconditionally stable and guarantee proper operation over the 70 MHz–250 MHz specified operating range. Circuit board layout is critical on this device, and proper PCB layout must be employed to achieve specified results.

2Analog Input 3 dB Bandwidth is determined by internal track-and-hold. The front-end attenuators have a bandwidth of 1 GHz. 3Measured real and imaginary values using Network Analyzer.

4Full-scale gain tolerance is the typical variation in gain at a given IF input frequency. The nominal value for full-scale input power is a function of frequency as shown in previous specification.

5Full-scale gain tolerance measured at 200 MHz analog input referenced to 6.7 dBm nominal full-scale input power. For the gain measurement test, the input signal level is set to –6 dBFS. Tuning port bandwidth is set to 50 MHz.

6Main channel set to full-scale input power. Diversity channel swept from –20 dBFS to –90 dBFS.

7Measurement includes thermal and quantization noise at 70 MHz analog input. Tuning port bandwidth is set to 50 MHz. 8Test tones at 160.05 MHz and 170.05 MHz.

9Measurements at –1 dFBS, –6 dBFS, and –10 dBFS are in highest attenuation mode, RSSI = 101.

10Each gain-range is checked at ~3 dB from RSSI trip point (not in hysteresis); nominally –16 dBFS (RSSI = 100), –22 dBFS (RSSI = 011), –28 dBFS (RSSI = 010), –35 dBFS (RSSI = 001).

11Measurement at –54 dBFS is in the lowest attenuation mode, RSSI = 000.

Specifications subject to change without notice.

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AD6600

ABSOLUTE MAXIMUM RATINGS1

Parameter	Min Max		Unit
ELECTRICAL
AVCC Voltage	0	7	V
DVCC Voltage	0	7	V
Analog Input Voltage2	0	AVCC	V
Analog Input Current2		25	mA
Digital Input Voltage3	0	AVCC	V
Output Current4		4	mA
Resonant Port Voltage5	0	AVCC	V
ENVIRONMENTAL6
Operating Temperature Range			°C
(Ambient)	–40	+85
Maximum Junction Temperature		150	°C
Lead Temperature (Soldering, 10 sec)		300	°C
Storage Temperature Range (Ambient)	–65	+150	°C

NOTES

1Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating

conditions for an extended period of time may affect device reliability. 2Pins AIN, AIN, BIN, BIN.

3Pins ENC, ENC, A_SEL, B_SEL.

4Pins D10:0, RSSI2:0, AB_OUT, CLK2×. 5Pins FLT, FLT.

6Typical thermal impedance (44-lead LQFP); θJC = 16°C/W, θJA = 55°C/W.

EXPLANATION OF TEST LEVELS

Test Level

I.100% Production Tested.

II.100% Production Tested at 25°C and guaranteed by design and characterization at temperature extremes.

IV. Parameter is guaranteed by design and characterization testing.

V. Parameter is a typical value only.

ORDERING GUIDE

	Temperature	Package	Package
Model	Range	Description	Option
AD6600AST	–40°C to	44-Terminal LQFP	ST-44
	+85°C	(Low-Profile Quad
	(Ambient)	Plastic Flatpack)
AD6600ST/PCB		Evaluation Board
		with AD6600AST

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6600 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

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