Analog Devices AD640TE-883B, AD640TD-883B, AD640JP-REEL7, AD640JP-REEL, AD640JP Datasheet

a		DC-Coupled Demodulating
		120 MHz Logarithmic Amplifier
		AD640*

FEATURES

Complete, Fully Calibrated Monolithic System Five Stages, Each Having 10 dB Gain, 350 MHz BW Direct Coupled Fully Differential Signal Path Logarithmic Slope, Intercept and AC Response are

Stable Over Full Military Temperature Range Dual Polarity Current Outputs Scaled 1 mA/Decade

Voltage Slope Options (1 V/Decade, 100 mV/dB, etc.) Low Power Operation (Typically 220 mW at 65 V)

Low Cost Plastic Packages Also Available APPLICATIONS

Radar, Sonar, Ultrasonic and Audio Systems Precision Instrumentation from DC to 120 MHz Power Measurement with Absolute Calibration Wide Range High Accuracy Signal Compression Alternative to Discrete and Hybrid IF Strips Replaces Several Discrete Log Amp ICs

PRODUCT DESCRIPTION

The AD640 is a complete monolithic logarithmic amplifier. A single AD640 provides up to 50 dB of dynamic range for frequencies from dc to 120 MHz. Two AD640s in cascade can provide up to 95 dB of dynamic range at reduced bandwidth. The AD640 uses a successive detection scheme to provide an output current proportional to the logarithm of the input voltage. It is laser calibrated to close tolerances and maintains high accuracy over the full military temperature range using supply voltages from ±4.5 V to ± 7.5 V.

The AD640 comprises five cascaded dc-coupled amplifier/limiter stages, each having a small signal voltage gain of 10 dB and a –3 dB bandwidth of 350 MHz. Each stage has an associated full-wave detector, whose output current depends on the absolute value of its input voltage. The five outputs are summed to provide the video output (when low-pass filtered) scaled at 1 mA per decade (50 µA per dB). On chip resistors can be used to convert this output current to a voltage with several convenient slope options. A balanced

signal output at +50 dB (referred to input) is provided to operate AD640s in cascade.

The logarithmic response is absolutely calibrated to within ±1 dB for dc or square wave inputs from ± 0.75 mV to ± 200 mV, with an intercept (logarithmic offset) at 1 mV dc. An integral X10 attenuator provides an alternative input range of ± 7.5 mV to

± 2 V dc. Scaling is also guaranteed for sinusoidal inputs.

The AD640B is specified for the industrial temperature range of –40°C to +85°C and the AD640T, available processed to MIL- STD-883B, for the military range of –55°C to +125°C. Both are available in 20-lead side-brazed ceramic DIPs or leadless chip carriers (LCC). The AD640J is specified for the commercial temperature range of 0°C to +70°C, and is available in both 20-lead plastic DIP (N) and PLCC (P) packages.

This device is now available to Standard Military Drawing (DESC) number 5962-9095501MRA and 5962-9095501M2A.

PRODUCT HIGHLIGHTS

1.Absolute calibration of a wideband logarithmic amplifier is unique. The AD640 is a high accuracy measurement device, not simply a logarithmic building block.

2.Advanced design results in unprecedented stability over the full military temperature range.

3.The fully differential signal path greatly reduces the risk of instability due to inadequate power supply decoupling and shared ground connections, a serious problem with commonly used unbalanced designs.

4.Differential interfaces also ensure that the appropriate ground connection can be chosen for each signal port. They further

increase versatility and simplify applications. The signal input impedance is ~500 kΩ in shunt with ~2 pF.

5.The dc-coupled signal path eliminates the need for numerous interstage coupling capacitors and simplifies logarithmic conversion of subsonic signals.

									(continued on page 4)
				FUNCTIONAL BLOCK DIAGRAM
		RG1 1kV	RG0	1kV RG2	LOG OUT	LOG COM	INTERCEPT POSITIONING BIAS		12	+VS
	18	17	16	15	14	13
COM
ATN OUT	19	FULL-WAVE		FULL-WAVE	FULL-WAVE		FULL-WAVE	FULL-WAVE
		DETECTOR		DETECTOR	DETECTOR		DETECTOR	DETECTOR
SIG +IN	20	10dB		10dB		10dB	10dB	10dB	11	SIG +OUT
SIG –IN	1								10	SIG –OUT
ATN LO	2	AMPLIFIER/LIMITER		AMPLIFIER/LIMITER	AMPLIFIER/LIMITER		AMPLIFIER/LIMITER	AMPLIFIER/LIMITER
	27V
ATN COM	3	270V							9	BL2
	30V
ATN COM	4	5	6	GAIN BIAS REGULATOR		7	SLOPE BIAS REGULATOR		8	ITC

ATN IN BL1	–V
	S

*Protected under U.S. patent number 4,990,803.

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: [phone]	World Wide Web Site: http://www.analog.com
Fax: [phone]	© Analog Devices, Inc., 1999

AD640–SPECIFICATIONS

DC SPECIFICATIONS (VS = 65 V, TA = +258C, unless otherwise noted)

Model				AD640J			AD640B			AD640T
Parameter		Conditions	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Units
TRANSFER FUNCTION	1			IOUT = IY LOG |VIN/VX| for VIN = ± 0.75 mV to ± 200 mV dc
SIGNAL INPUTS (Pins 1, 20)
Input Resistance		Differential		500			500			500		kΩ
Input Offset Voltage		Differential		50	500		50	200		50	200	µV
vs. Temperature				0.8			0.8			0.8		µV/°C
Over Temperature		TMIN to TMAX									300	µV
vs. Supply				2			2			2		µV/V
Input Bias Current				7	25		7	25		7	25	µA
Input Bias Offset				1			1			1		µA
Common-Mode Range			–2		+0.3	–2		+0.3	–2		+0.3	V
INPUT ATTENUATOR
(Pins 2, 3, 4, 5 and 19)
Attenuation2		Pin 5 to Pin 19		20			20			20		dB
Input Resistance		Pins 5 to 3/4		300			300			300		Ω
SIGNAL OUTPUT (Pins 10, 11)
Small Signal Gain3				50			50			50		dB
Peak Differential Output4				±180			± 180			± 180		mV
Output Resistance		Either Pin to COM		75			75			75		Ω
Quiescent Output Voltage		Either Pin to COM		–90			–90			–90		mV
LOGARITHMIC OUTPUT5 (Pin 14)
Voltage Compliance Range			–0.3		+VS –1	–0.3		+VS –1	–0.3		VS –1	V
Slope Current, IY			0.95	1.00	1.05	0.98	1.00	1.02	0.98	1.00	1.02	mA
Accuracy vs. Temperature				0.002			0.002			0.002		%/°C
		TMIN to TMAX							0.98		1.02	mA
Accuracy vs. Supply		+VS = 4.5 V to 7.5 V		0.08	1.0		0.08	0.4		0.08	0.4	%/V
Intercept Voltage6, VX			0.85	1.00	1.15	0.95	1.00	1.05	0.95	1.00	1.05	mV
vs. Temperature				0.5			0.5			0.5		µV/°C
Over Temperature		TMIN to TMAX							0.90		1.10	mV
vs. Supply		±VS = 4.5 V to 7.5 V		2			2			2		µV/V
Logarithmic Offset
(Alt. Definition of VX)			–61.5	–60.0	–58.7	–60.5	–60.0	–59.5	–60.5	–60.0	–59.5	dBV
vs. Temperature				0.004			0.004			0.004		dB/°C
Over Temperature		TMIN to TMAX							–60.9		–59.1	dB
vs. Supply		±VS = 4.5 V to 7.5 V		0.017			0.017			0.017		dB/V
Intercept Voltage Using Attenuator			8.25	10.0	11.75	9.0	10.0	11.0	9.0	10.0	11.0	mV
Zero Signal Output Current7				–0.2			–0.2			–0.2		mA
ITC Disabled		Pin 8 to COM		–0.27			–0.27			–0.27		mA
Maximum Output Current				2.3			2.3			2.3		mA
APPLICATIONS RESISTORS
(Pins 15, 16, 17)				1.000		0.995	1.000	1.005	0.995	1.000	1.005	kΩ
DC LINEARITY
VIN ±1 mV to ± 100 mV				0.35	1.2		0.35	0.6		0.35	0.6	dB
TOTAL ABSOLUTE DC
ACCURACY
VIN = ± 1 mV to ±100 mV8				0.55	2		0.55	0.9		0.55	0.9	dB
Over Temperature		TMIN to TMAX			3			1.7			1.8	dB
Over Supply Range		±VS = 4.5 V to 7.5 V			2			1.0			1.0	dB
VIN = ± 0.75 mV to ±200 mV				1.0	3		1.0	2.0		1.0	2.0	dB
Using Attenuator
VIN = ± 10 mV to ± 1 V				0.4	2.5		0.4	1.5		0.4	1.5	dB
Over Temperature		TMIN to TMAX		0.6	3		0.6	2.0		0.6	2.0	dB
VIN = ± 7.5 mV to 2 V				1.2	3.5		1.2	2.5		1.2	2.5	dB
POWER REQUIREMENTS
Voltage Supply Range			64.5		67.5	64.5		67.5	64.5		67.5	V
Quiescent Current9
+VS (Pin 12)		TMIN to TMAX		9	15		9	15		9	15	mA
–VS (Pin 7)		TMIN to TMAX		35	60		35	60		35	60	mA

–2–

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												AD640
AC SPECIFICATIONS (VS = 65 V, TA = +258C, unless otherwise noted)
Model			AD640J				AD640B			AD640T
Parameter	Conditions	Min	Typ	Max		Min	Typ	Max	Min	Typ	Max		Units
SIGNAL INPUTS (Pins 1, 20)
Input Capacitance	Either Pin to COM		2				2			2			pF
Noise Spectral Density	1 kHz to 10 MHz		2				2			2			nV/√Hz
Tangential Sensitivity	BW = 100 MHz		–72				–72			–72			dBm
3 dB BANDWIDTH
Each Stage			350				350			350			MHz
All Five Stages	Pins 1 & 20 to 10 & 11		145				145			145			MHz
LOGARITHMIC OUTPUTS5
Slope Current, IY
f< = 1 MHz		0.96	1.0	1.04		0.98	1.0	1.02	0.98	1.0	1.02		mA
f = 30 MHz		0.88	0.94	1.00		0.91	0.94	0.97	0.91	0.94	0.97		mA
f = 60 MHz		0.82	0.90	0.98		0.86	0.90	0.94	0.86	0.90	0.94		mA
f = 90 MHz			0.88				0.88			0.88			mA
f = 120 MHz			0.85				0.85			0.85			mA
Intercept, Dual AD640s10, 11
f< = 1 MHz		–90.6	–88.6	–86.6		–89.6	–88.6	–87.6	–89.6	–88.6	–87.6		dBm
f = 30 MHz			–87.6				–87.6			–87.6			dBm
f = 60 MHz			–86.3				–86.3			–86.3			dBm
f = 90 MHz			–83.9				–83.9			–83.9			dBm
f = 120 MHz			–80.3				–80.3			–80.3			dBm
AC LINEARITY
–40 dBm to –2 dBm12	f = 1 MHz		0.5	2.0			0.5	1.0		0.5	1.0		dB
–35 dBm to –10 dBm12	f = 1 MHz		0.25	1.0			0.25	0.5		0.25	0.5		dB
–75 dBm to 0 dBm10	f = 1 MHz		0.75	3.0			0.75	1.5		0.75	1.5		dB
–70 dBm to –10 dBm10	f = 1 MHz		0.5	2.0			0.5	1.0		0.5	1.0		dB
–75 dBm to +15 dBm13	f = 10 kHz		0.5	3.0			0.5	1.5		0.5	1.5		dB
PACKAGE OPTION
20-Lead Ceramic DIP Package (D)							AD640BD			AD640TD
20-Terminal Ceramic LCC (E)							AD640BE			AD640TE
20-Lead Plastic DIP Package (N)			AD640]N
20-Lead Plastic Leaded Chip Carrier (P)			AD640JP				AD640BP
NUMBER OF TRANSISTORS			155				155			155

NOTES

1Logarithms to base 10 are used throughout. The response is independent of the sign of V IN.

2Attenuation ratio trimmed to calibrate intercept to 10 mV when in use. It has a temperature coefficient of +0.30%/ °C. 3Overall gain is trimmed using a ± 200 µV square wave at 2 kHz, corrected for the onset of compression.

4The fully limited signal output will appear to be a square wave; its amplitude is proportional to absolute temperature.

5Currents defined as flowing into Pin 14. See FUNDAMENTALS OF LOGARITHMIC CONVERSION for full explanation of scaling concepts. Slope is measured by linear regression over central region of transfer function.

6The logarithmic intercept in dBV (decibels relative to 1 V) is defined as 20 LOG10 (VX/1 V).

7The zero-signal current is a function of temperature unless internal temperature compensation (ITC) pin is grounded.

8Operating in circuit of Figure 24 using ± 0.1% accurate values for RLA and RLB. Includes slope and nonlinearity errors. Input offset errors also included for VIN >3 mV dc, and over the full input range in ac applications.

9Essentially independent of supply voltages.

10Using the circuit of Figure 27, using cascaded AD640s and offset nulling. Input is sinusoidal, 0 dBm in 50 Ω = 223 mV rms.

11For a sinusoidal signal (see EFFECT OF WAVEFORM ON INTERCEPT). Pin 8 on second AD640 must be grounded to ensure temperature stability of intercept for dual AD640 system.

12Using the circuit of Figure 24, using single AD640 and offset nulling. Input is sinusoidal, 0 dBm in 50 Ω = 223 mV rms. 13Using the circuit of Figure 32, using cascaded AD640s and attenuator. Square wave input.

All min and max specifications are guaranteed, but only those in boldface are 100% tested on all production units. Results from those tests are used to calculate outgoing quality levels.

Specifications subject to change without notice.

THERMAL CHARACTERISTICS

	uJC (8C/W)	uJA (8C/W)
20-Lead Ceramic DIP Package (D-20)	25	85
20-Terminal Ceramic LCC (E-20A)	25	85
20-Lead Plastic DIP Package (N-20)	24	61
20-Lead Plastic Leaded Chip Carrier (P-20A)	28	75

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–3–

AD640

(continued from page 1)

6.The low input offset voltage of 50 V (200 V max) ensures good accuracy for low level dc inputs.

7.Thermal recovery “tails,” which can obscure the response when a small signal immediately follows a high level input, have been minimized by special attention to design details.

8.The noise spectral density of 2 nV/√Hz results in a noise floor of ~23 V rms (–80 dBm) at a bandwidth of 100 MHz. The dynamic range using cascaded AD640s can be extended to 95 dB by the inclusion of a simple filter between the two devices.

CHIP DIMENSIONS AND

BONDING DIAGRAM

Dimensions shown in inches and (mm).

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7.5 V Input Voltage (Pin 1 or Pin 20 to COM) . . . . –3 V to +300 mV Attenuator Input Voltage (Pin 5 to Pin 3/4) . . . . . . . . . . . ±4 V Storage Temperature Range D, E . . . . . . . . . –65°C to +150°C Storage Temperature Range N, P . . . . . . . . . –65°C to +125°C Ambient Temperature Range, Rated Performance

Industrial, AD640B . . . . . . . . . . . . . . . . . . . –40°C to +85°C Military, AD640T . . . . . . . . . . . . . . . . . . . –55°C to +125°C Commercial, AD640J . . . . . . . . . . . . . . . . . . . 0°C to +70°C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING GUIDE

	Temperature	Package	Package
Model	Range	Description	Option
AD640JN	0°C to +70°C	20-Lead Plastic DIP	N-20
AD640JP	0°C to +70°C	20-Lead PLCC	P-20A
AD640BD	–40°C to +85°C	20-Lead Ceramic DIP	D-20
AD640BE	–40°C to +85°C	20-Terminal Ceramic
	–40°C to +85°C	LCC	E-20A
AD640BP		20-Lead PLCC	P-20A
AD640TD/883B	–55°C to +125°C	20-Lead Ceramic DIP	D-20
5962-9095501MRA	–55°C to +125°C	20-Lead Ceramic DIP	D-20
AD640TE/883B	–55°C to +125°C	20-Terminal Ceramic
	–55°C to +125°C	LCC	E-20A
5962-9095501M2A		20-Terminal Ceramic
	–55°C to +125°C	LCC	E-20A
AD640TCHIPS		Die
AD640EB	0°C to +70°C	Evaluation Board
AD640JP-REEL		13" Tape and Reel	P-20A
AD640JP-REEL7	0°C to +70°C	7" Tape and Reel	P-20A

							CONNECTION DIAGRAMS
20-Lead Ceramic DIP (D) Package							20-Lead PLCC (P) Package								20-Terminal Ceramic LCC (E) Package
20-Lead Plastic DIP (N) Package
SIG –IN						SIG +IN		ATNCOM	ATNLO	SIG–IN	SIG+IN	ATNOUT					ATNCOM	ATNLO		SIG–IN	SIG+IN	ATNOUT
	1				20
ATN LO						ATN OUT
	2				19			3	2	1	20	19					3	2	1		20	19
ATN COM						CKT COM
	3				18		ATN COM 4			PIN 1			18	CKT COM	ATN COM 4								18	CKT COM
ATN COM						RG1
	4				17		ATN IN	5		IDENTIFIER			17	RG1	ATN IN 5								17	RG1
																		AD640
ATN IN		AD640				RG0
	5				16		BL1	6	AD640				16	RG0	BL1 6								16	RG0
		TOP VIEW							TOP VIEW									TOP VIEW
BL1	6				15	RG2	–V						15	RG2	–V 7		(Not to Scale)						15	RG2
		(Not to Scale)						7	(Not to Scale)
–V	7				14	LOG OUT	S								S								14	LOG OUT
															ITC	8
S							ITC	8					14	LOG OUT
ITC						LOG COM
	8				13			9	10	11	12	13					9	10	11		12	13
								BL2	SIG–OUT	SIG+OUT	+V	LOGCOM
																	BL2	–OUTSIG		+OUTSIG	+V	COMLOG
BL2	9				12	+VS					S										S
SIG –OUT	10				11	SIG +OUT

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD640 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. C

	1.015
mA	1.010
	1.005
–
CURRENT	1
SLOPE	0.995
	0.990
	0.985
	0.980
					0	20	40	60	80 100 120 140
	–60 –40 –20

TEMPERATURE –8C

Figure 1. Slope Current, IY vs. Temperature

	1.015
– mV	1.010
VOLTAGE	1.005
INTERCEPT	1.000
	0.990
	0.995
	0.985
			5.0		5.5		6.0		6.5		7.0		7.5
	4.5

POWER SUPPLY VOLTAGES –6Volts

Figure 4. Intercept Voltage, VX, vs. Supply Voltages

	2.4				2	dB
					1	–
	2.2
					0	ERROR
	2.0
mA
	1.8
	1.6
–
	1.4
CURRENT
	1.2
	1.0
	0.8
OUTPUT	0.6
	0.4
	0.2
	0
	–0.2
	–0.4
	0.1	1.0	10.0	100.0	1000.0
		INPUT VOLTAGE – mV
			(EITHER SIGN)

Figure 7. DC Logarithmic Transfer Function and Error Curve for Single AD640

Typical DC Performance Characteristics–AD640

	1.20
	1.15
– mV	1.10
	1.05
INTERCEPT
	1.00
	0.95
	0.90
	0.85
	–60		–40 –20			0	20	40	60	80 100 120 140
					TEMPERATURE –8C

Figure 2. Intercept Voltage, VX, vs. Temperature

		14
		13
	– mV	12
		11
	INTERCEPT
		10
		9

8

7 –60 –40 –20 0 20 40 60 80 100 120 140

TEMPERATURE –8C

Figure 5. Intercept Voltage (Using Attenuator) vs. Temperature

	2.5
– dB	2.0
ERROR	1.5
ABSOLUTE	1.0
	0.5
	0	0	20	40	60	80 100 120 140
	–60 –40 –20
	TEMPERATURE –8C

Figure 8. Absolute Error vs. Temperature, VIN = 61 mV to 6100 mV

	1.006
	1.004
– mA	1.002
CURRENT	1.000
SLOPE	0.998
	0.996

0.994

4.5

5.0

5.5

6.0

6.5

7.0

7.5

POWER SUPPLY VOLTAGES –6Volts

Figure 3. Slope Current, IY vs. Supply Voltages

mV	+0.4
–
VOLTAGE	+0.3
	+0.2	INPUT OFFSET VOLTAGE
		DEVIATION WILL BE WITHIN
OFFSET		SHADED AREA.
	+0.1
INPUT	0
	–0.1
OF
DEVIATION	–0.2
	–0.3		0	20	40	60	80 100 120 14
	–60 –40 –20
		TEMPERATURE –8C

Figure 6. Input Offset Voltage Deviation vs. Temperature

	2.5
– dB	2.0
ERROR	1.5
ABSOLUTE	1.0
	0.5
	0	0	20	40	60	80 100 120 14
	–60 –40 –20
	TEMPERATURE –8C

Figure 9. Absolute Error vs. Temperature, Using Attenuator. VIN = 610 mV to 61 V, Pin 8 Grounded to Disable ITC Bias

REV. C

–5–