THS1206 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
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features |
applications |
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D High-Speed 6 MSPS ADC |
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Radar Applications |
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D 4 Single-Ended or 2 Differential Inputs |
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Communications |
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D Simultaneous Sampling of 4 Single-Ended |
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Control Applications |
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Signals or 2 Differential Signals or |
D High-Speed DSP Front-End |
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Combination of Both |
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Automotive Applications |
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D Differential Nonlinearity Error: ±1 LSB |
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D Integral Nonlinearity Error: ±1.5 LSB |
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DA PACKAGE |
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D Signal-to-Noise and Distortion Ratio: 68 dB |
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(TOP VIEW) |
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at fI = 2 MHz |
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D0 |
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AINP |
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1 |
32 |
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D Auto-Scan Mode for 2, 3, or 4 Inputs |
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D1 |
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31 |
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AINM |
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D 3-V or 5-V Digital Interface Compatible |
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D2 |
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3 |
30 |
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BINP |
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D Low Power: 216 mW Max |
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D3 |
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BINM |
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D 5-V Analog Single Supply Operation |
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D4 |
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28 |
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REFIN |
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D5 |
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REFOUT |
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D |
Internal Voltage References . . . 50 PPM/°C |
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6 |
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BVDD |
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REFP |
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and ±5% Accuracy |
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REFM |
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D |
Glueless DSP Interface |
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BGND |
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D6 |
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AGND |
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Parallel C/DSP Interface |
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D |
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D7 |
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AVDD |
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Integrated FIFO |
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D |
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D8 |
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CS0 |
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D Available in TSSOP Package |
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D9 |
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CS1 |
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D10/RA0 |
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13 |
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WR |
(R/W) |
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description |
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D11/RA1 |
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RD |
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CONV_CLK |
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DVDD |
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The THS1206 is a CMOS, low-power, 12-bit, |
(CONVST) |
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15 |
18 |
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DATA_AV |
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DGND |
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6 MSPS analog-to-digital converter (ADC). The |
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speed, resolution, bandwidth, and single-supply |
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operation are suited for applications in radar, |
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imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error |
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correction logic provides for no missing codes over the full operating temperature range. Internal control |
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registers are used to program the ADC into the desired mode. The THS1206 consists of four analog inputs, |
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which are sampled simultaneously. These inputs can be selected individually and configured to single-ended |
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or differential inputs. An integrated 16 word deep FIFO allows the storage of data in order to take the load off |
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of the processor connected to the ADC. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided. |
An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. Two different conversion modes can be selected. In single conversion mode, a single and simultaneous conversion of up to four inputs can be initiated by using the single conversion start signal (CONVST). The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. In continuous conversion mode, an external clock signal is applied to the CONV_CLK input of the THS1206. The internal clock oscillator is switched off in continuous conversion mode.
The THS1206C is characterized for operation from 0°C to 70°C, the THS1206I is characterized for operation from ±40°C to 85°C, the THS1206Q is characterized to meet the rigorous requirements of the automotive environment from ±40°C to 125°C, and the THS1206M is characterized for operation over the full military temperature range of ±55°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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THS1206 |
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12-BIT 6 MSPS, SIMULTANEOUS SAMPLING |
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ANALOG-TO-DIGITAL CONVERTERS |
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SLAS217D ± MAY 1999 ± REVISED APRIL 2000 |
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AVAILABLE OPTIONS |
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PACKAGED DEVICE |
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TA |
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TSSOP |
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(DA) |
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0°C to 70°C |
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THS1206CDA |
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±40°C to 85°C |
THS1206IDA |
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±40°C to 125°C |
THS1206QDA |
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±55°C to 125°C |
THS1206MDA |
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functional block diagram |
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AVDD |
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DVDD |
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REFP |
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3.5 V |
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2.5 V |
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1.225 V |
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REFOUT |
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1.5 V |
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REF |
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REFM |
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REFIN |
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AINP |
S/H |
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VREFM |
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DATA_AV |
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VREFP |
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AINM |
S/H |
Single |
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BVDD |
12 Bit |
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Ended |
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FIFO |
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D0 |
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and/or |
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Pipeline |
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± |
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16 |
× 12 |
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D1 |
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Differential |
ADC |
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BINP |
S/H |
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D2 |
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MUX |
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Buffers |
D3 |
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D4 |
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D5 |
BINM |
S/H |
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D6 |
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D7 |
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D8 |
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D9 |
CONV_CLK (CONVST) |
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D10/RA0 |
CS0 |
Logic |
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D11/RA1 |
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CS1 |
and |
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Control |
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BGND |
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RD |
Control |
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Register |
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WR (R/W) |
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AGND |
DGND |
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2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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THS1206 |
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12-BIT 6 MSPS, SIMULTANEOUS SAMPLING |
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ANALOG-TO-DIGITAL CONVERTERS |
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SLAS217D ± MAY 1999 ± REVISED APRIL 2000 |
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Terminal Functions |
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TERMINAL |
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I/O |
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DESCRIPTION |
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NAME |
NO. |
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AINP |
32 |
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Analog input, single-ended or positive input of differential channel A |
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AINM |
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Analog input, single-ended or negative input of differential channel A |
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BINP |
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Analog input, single-ended or positive input of differential channel B |
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BINM |
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Analog input, single-ended or negative input of differential channel B |
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AVDD |
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Analog supply voltage |
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AGND |
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Analog ground |
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BVDD |
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Digital supply voltage for buffer |
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Digital ground for buffer |
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CONV_CLK |
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Digital input. This input is used to apply an external conversion clock in continuous conversion |
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(CONVST) |
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mode. In single conversion mode, this input functions as the conversion start (CONVST) input. |
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A high to low transition on this input holds simultaneously the selected analog input channels |
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and initiates a single conversion of all selected analog inputs. |
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22 |
I |
Chip select input (active low) |
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CS0 |
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CS1 |
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Chip select input (active high) |
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DATA_AV |
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Data available signal, which can be used to generate an interrupt for processors and as a level |
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information of the internal FIFO. This signal can be configured to be active low or high and can |
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be configured as a static level or pulse output. See Table 14. |
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DGND |
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Digital ground. Ground reference for digital circuitry. |
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DVDD |
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Digital supply voltage |
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D0 ± D9 |
1±6, 9±12 |
I/O/Z |
Digital input, output; D0 = LSB |
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D10/RA0 |
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I/O/Z |
Digital input, output. The data line D10 is also used as an address line (RA0) for the control |
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register. This is required for writing to the control register 0 and control register 1. See Table 8. |
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D11/RA1 |
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I/O/Z |
Digital input, output (D11 = MSB). The data line D11 is also used as an address line (RA1) for |
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the control register. This is required for writing to control register 0 and control register 1. See |
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Table 8. |
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REFIN |
28 |
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Common-mode reference input for the analog input channels. It is recommended that this pin |
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be connected to the reference output REFOUT. |
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REFP |
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Reference input, requires a bypass capacitor of 10 F to AGND in order to bypass the internal |
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reference voltage. An external reference voltage at this input can be applied. This option can |
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be programmed through control register 0. See Table 9. |
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REFM |
25 |
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Reference input, requires a bypass capacitor of 10 F to AGND in order to bypass the internal |
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reference voltage. An external reference voltage at this input can be applied. This option can |
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be programmed through control register 0. See Table 9. |
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REFOUT |
27 |
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Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 A. The |
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reference output requires a capacitor of 10 F to AGND for filtering and stability. |
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19 |
I |
The |
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input is used only if the |
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input is configured as a write only input. In this case, it is a |
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RD |
RD |
WR |
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digital input, active low as a data read select from the processor. See timing section. |
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² |
20 |
I |
This input is programmable. It functions as a read-write input R/W and can also be configured |
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WR |
(R/W) |
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as a write-only input WR, which is active low and used as data write select from the processor. |
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In this case, the RD input is used as a read input from the processor. See timing section. |
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² The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
3 |
THS1206
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS217D ± MAY 1999 ± REVISED APRIL 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)²
Supply voltage range, DGND to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . ±0.3 V to 6.5 V |
BGND to BVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . ±0.3 V to 6.5 V |
AGND to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . ±0.3 V to 6.5 V |
Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
AGND ± 0.3 V to AVDD + 1.5 V |
Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±0.3 + AGND to AVDD + 0.3 V |
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±0.3 V to BVDD/DVDD + 0.3 V |
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . ±55°C to 150°C |
Operating free-air temperature range,TA THS1206C . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . 0°C to 70°C |
THS1206I . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . ±40°C to 85°C |
THS1206Q . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . ±40°C to 125°C |
THS1206M . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . ±55°C to 125°C |
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . ±65°C to 150°C |
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . 260°C |
²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE |
TA ≤ 25°C |
DERATING FACTOR |
TA = 70°C |
TA = 85°C |
TA = 125°C |
|
POWER RATING |
ABOVE T = 25°C³ |
POWER RATING |
POWER RATING |
POWER RATING |
||
|
||||||
|
|
A |
|
|
|
|
DA |
1453 mW |
11.62 mW/°C |
930 mW |
756 mW |
291 mW |
³This is the inverse of the traditional junction-to-ambient thermal resistance (RθJA). Thermal resistances are not production tested and are for informational purposes only.
recommended operating conditions power supply
|
|
MIN |
NOM |
MAX |
UNIT |
|
|
|
|
|
|
|
AVDD |
4.75 |
5 |
5.25 |
|
Supply voltage |
DVDD |
3 |
3.3 |
5.25 |
V |
|
BVDD |
3 |
3.3 |
5.25 |
|
analog and reference inputs
|
MIN |
NOM |
MAX |
UNIT |
|
|
|
|
|
Analog input voltage in single-ended configuration |
VREFM |
|
VREFP |
V |
Common-mode input voltage VCM in differential configuration |
1 |
2.5 |
4 |
V |
External reference voltage,VREFP (optional) |
|
3.5 |
AVDD±1.2 |
V |
External reference voltage, VREFM (optional) |
1.4 |
1.5 |
|
V |
Input voltage difference, REFP ± REFM |
|
2 |
|
V |
4 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
THS1206 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS217D ± MAY 1999 ± REVISED APRIL 2000
recommended operating conditions (continued) digital inputs
|
|
MIN |
NOM |
MAX |
UNIT |
|
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|
|
|
|
High-level input voltage, VIH |
BVDD = 3.3 V |
2 |
|
|
V |
BVDD = 5.25 V |
2.6 |
|
|
V |
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|
|||
Low-level input voltage, VIL |
BVDD = 3.3 V |
|
|
0.6 |
V |
BVDD = 5.25 V |
|
|
0.6 |
V |
|
|
|
|
|||
Input CONV_CLK frequency |
DVDD = 3 V to 5.25 V |
0.1 |
|
6 |
MHz |
CONV_CLK pulse duration, clock high, tw(CONV_CLKH) |
DVDD = 3 V to 5.25 V |
80 |
83 |
5000 |
ns |
CONV_CLK pulse duration, clock low, tw(CONV_CLKL) |
DVDD = 3 V to 5.25 V |
80 |
83 |
5000 |
ns |
|
THS1206CDA |
0 |
|
70 |
|
|
|
|
|
|
|
Operating free-air temperature, TA |
THS1206IDA |
±40 |
|
85 |
°C |
|
|
|
|
||
THS1206QDA |
±40 |
|
125 |
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|||
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THS1206MDA |
±55 |
|
125 |
|
electrical characteristics over recommended operating conditions, VREF = internal (unless otherwise noted)
digital specifications
|
PARAMETER |
TEST CONDITIONS |
MIN |
TYP MAX |
UNIT |
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Digital inputs |
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IIH |
High-level input current |
DVDD = digital inputs |
|
±50 |
50 |
A |
|
IIL |
Low-level input current |
Digital input = 0 V |
|
±50 |
50 |
A |
|
Ci |
Input capacitance |
|
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|
5 |
pF |
Digital outputs |
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VOH |
High-level output voltage |
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BVDD±0.5 |
|
V |
|
BV |
= 3.3 V, |
BVDD±0.5 |
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|||
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IOH = ±50 A |
DD |
|
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VOL |
Low-level output voltage |
BVDD |
= 5 V |
|
0.4 |
V |
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||||||
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0.4 |
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IOZ |
High-impedance-state output current |
CS1 = DGND, CS0 = DVDD |
±10 |
10 |
A |
||
CO |
Output capacitance |
|
|
|
|
5 |
pF |
CL |
Load capacitance at databus D0 ± D11 |
|
|
|
|
30 |
pF |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
5 |
THS1206
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS217D ± MAY 1999 ± REVISED APRIL 2000
electrical characteristics over recommended operating conditions, VREF = internal (unless otherwise noted) (continued)
dc specifications
|
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
||
|
|
|
|
|
|
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|
|
Resolution |
|
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12 |
|
|
Bits |
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Accuracy |
|
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Integral nonlinearity, INL |
C and I suffix |
|
|
|
±1.5 |
LSB |
|
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||
|
Q and M suffix |
|
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±1.8 |
|||
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Differential nonlinearity, DNL |
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±1 |
LSB |
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Offset error |
After calibration in single-ended mode |
±15² |
|
15² |
mV |
||
|
After calibration in differential mode |
±5² |
|
5² |
mV |
|||
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||||||
|
Gain error |
|
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|
1% |
FSR |
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Analog input |
|
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Input capacitance |
|
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|
15 |
|
pF |
|
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|
Input leakage current |
VAIN = VREFM to VREFP |
|
|
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±10 |
A |
|
Internal voltage reference |
|
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Accuracy, VREFP |
C and I suffix |
|
3.33 |
3.5 |
3.67 |
V |
|
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||
|
Q and M suffix |
|
3.3 |
3.5 |
3.7 |
|||
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|||||
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Accuracy, VREFM |
C and I suffix |
|
1.42 |
1.5 |
1.58 |
V |
|
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|
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||
|
Q and M suffix |
|
1.3 |
1.5 |
1.7 |
|||
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|||||
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Temperature coefficient |
|
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|
50 |
|
PPM/°C |
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Reference noise |
|
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|
100 |
|
V |
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Accuracy, REFOUT |
C and I suffix |
|
2.475 |
2.5 |
2.525 |
V |
|
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|
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||
|
Q and M suffix |
|
2.3 |
2.5 |
2.7 |
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|||||
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Power supply |
|
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IDDA |
Analog supply current |
AVDD =5 V, BVDD = DVDD = 3.3 V |
|
36 |
40 |
mA |
||
IDDD |
Digital supply voltage |
AVDD = 5 V, BVDD = DVDD = 3.3 V |
|
0.5 |
1 |
mA |
||
IDDB |
Buffer supply voltage |
AVDD = 5 V, BVDD = DVDD = 3.3 V |
|
1.5 |
4 |
mA |
||
IDD_P |
Supply current in power-down mode |
AVDD = 5 V, |
|
C and I suffix |
|
|
7 |
mA |
BVDD = DVDD = 3.3 V |
|
Q and M suffix |
|
|
10 |
|||
|
|
|
|
|
|
|||
|
Power dissipation |
AVDD = 5 V, DVDD = BVDD = 3.3 V |
|
186 |
216 |
mW |
||
|
Power dissipation in power down |
AVDD = 5 V, DVDD = BVDD = 3.3 V |
|
30 |
|
mW |
² Not production tested for M and Q suffix devices.
6 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
THS1206 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS217D ± MAY 1999 ± REVISED APRIL 2000
electrical characteristics over recommended operating conditions, VREF = internal, fs = 6 MHz, fI = 2 MHz at ±1dBFS (unless otherwise noted) (continued)
ac specifications, AVDD = 5 V, BVDD = DVDD = 3.3 V, CL < 30 pF
|
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
|
|
|
|
|
|
|
|
|
SINAD |
Signal-to-noise ratio + distortion |
Differential mode |
63 |
68 |
|
dB |
|
|
|
|
|
|
|
||
Single-ended mode (see Note 1) |
|
64 |
|
dB |
|||
|
|
|
|
||||
|
|
|
|
|
|
|
|
SNR |
Signal-to-noise ratio |
Differential mode |
64 |
69 |
|
dB |
|
|
|
|
|
|
|
||
Single-ended mode (see Note 1) |
|
65 |
|
dB |
|||
|
|
|
|
||||
|
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|
|
|
|
Differential mode |
C and I suffix |
|
±73 |
±69 |
|
|
|
|
|
|
|
|
|
THD |
Total harmonic distortion |
Q and M suffix |
|
±73 |
±67 |
dB |
|
|
|
||||||
|
|
|
|
|
|||
Single-ended mode |
C and I suffix |
|
±73 |
±69 |
|||
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|
||||
|
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|
Q and M suffix |
|
±73 |
±67 |
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
ENOB |
Effective number of bits |
Differential mode |
10.3 |
11 |
|
Bits |
|
(SNR) |
Single-ended mode (see Note 1) |
|
10.4 |
|
Bits |
||
|
|
|
|||||
|
|
|
|
|
|
|
|
SFDR Spurious free dynamic range |
Differential mode |
68 |
75 |
|
dB |
||
|
|
|
|
|
|
||
Single-ended mode |
68 |
75 |
|
dB |
|||
|
|
|
|||||
|
|
|
|
|
|
|
|
Analog Input |
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
Full-power bandwidth with a source impedance of |
FS sinewave, ±3 dB |
|
96 |
|
MHz |
|
|
150 Ω in differential configuration. |
|
|
||||
|
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|
|
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|
|
|
|
|
|
|
|
|
Full-power bandwidth with a source impedance of |
FS sinewave, ±3 dB |
|
54 |
|
MHz |
|
|
150 Ω in single-ended configuration. |
|
|
||||
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
Small-signal bandwidth with a source impedance |
100 mVpp sinewave, ±3 dB |
|
96 |
|
MHz |
|
|
of 150 Ω in differential configuration. |
|
|
||||
|
|
|
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|
|
|
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|
|
|
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|
|
|
|
Small-signal bandwidth with a source impedance |
100 mVpp sinewave, ±3 dB |
|
54 |
|
MHz |
|
|
of 150 Ω in single-ended configuration. |
|
|
||||
|
|
|
|
|
|
|
NOTE 1: The SNR (ENOB) and SINAD is degraded typically by 2 dB in single-ended mode when the reading of data is asynchronous to the sampling clock.
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
7 |
THS1206
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS217D ± MAY 1999 ± REVISED APRIL 2000
timing specifications, AVDD = 5 V, BVDD = DVDD = 3.3 V, VREF = internal, CL < 30 pF
|
PARAMETER |
TEST CONDITIONS |
MIN TYP MAX |
UNIT |
|
|
|
|
|
td(DATA_AV) |
Delay time |
|
5 |
ns |
td(o) |
Delay time |
|
5 |
ns |
tpipe |
Latency |
|
5 |
CONV |
|
CLK |
|||
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|
|
timing specification of the single conversion mode²
|
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
|||
|
|
|
|
|
|
|
|
|
|
tc |
Clock cycle of the internal clock oscillator |
|
|
159 |
167 |
175 |
ns |
||
tw1 |
Pulse width, |
|
|
|
|
1.5×tc |
|
|
ns |
CONVST |
|
|
|
|
|
||||
tdA |
Aperture time |
|
|
|
1 |
|
ns |
||
|
|
|
|
1 analog input |
|
2×tc |
|
|
ns |
t2 |
Time between consecutive start of single conversion |
2 analog inputs |
|
3×tc |
|
|
|||
|
|
|
|
||||||
3 analog inputs |
|
4×tc |
|
|
ns |
||||
|
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|||
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4 analog inputs |
|
5×tc |
|
|
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|
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|
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|
||
|
|
|
|
1 analog input, |
TL = 1 |
|
|
6×tc |
ns |
|
Delay time, DATA_AV becomes active for the trigger |
2 analog inputs, TL = 2 |
|
|
7×tc |
||||
|
|
|
|
||||||
|
level condition: TRIG0 = 0, TRIG1 = 0 |
3 analog inputs, TL = 3 |
|
|
8×tc |
ns |
|||
|
|
|
|
4 analog inputs, |
TL = 4 |
|
|
9×tc |
|
|
|
|
|
|
|
|
|||
|
|
|
|
1 analog input, |
TL = 4 |
|
|
3×t2 +6×tc |
ns |
td(DATA_AV) |
Delay time, DATA_AV becomes active for the trigger |
2 analog inputs, |
TL = 4 |
|
|
t2 +7×tc |
|||
|
|
|
|||||||
level condition: TRIG0 = 1, TRIG1 = 0 |
3 analog inputs, |
TL = 6 |
|
|
t2 +8×tc |
ns |
|||
|
|
|
|||||||
|
|
|
|
4 analog inputs, |
TL = 8 |
|
|
t2 +9×tc |
|
|
|
|
|
|
|
|
|||
|
|
|
|
1 analog input, |
TL = 8 |
|
|
7×t2 +6×tc |
ns |
|
Delay time, DATA_AV becomes active for the trigger |
2 analog inputs, TL = 8 |
|
|
3×t2 +7×tc |
||||
|
|
|
|
||||||
|
level condition: TRIG0 = 0, TRIG1 = 1 |
3 analog inputs, TL = 9 |
|
|
2×t2 +8×tc |
ns |
|||
|
|
|
|
4 analog inputs, |
TL = 12 |
|
|
2×t2 +9×tc |
|
|
|
|
|
|
|
|
|||
|
Delay time, DATA_AV becomes active for the trigger |
1 analog input, |
TL = 14 |
|
|
13×t2 +6×tc |
ns |
||
td(DATA_AV) |
2 analog inputs, TL = 12 |
|
|
5×t2 +7×tc |
|||||
level condition: TRIG0 = 1, TRIG1 = 1 |
|
|
|
||||||
|
3 analog inputs, TL = 12 |
|
|
3×t2 +8×tc |
ns |
||||
|
|
|
|
|
|
² Timing parameters are ensured by design but are not tested.
8 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
THS1206 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS217D ± MAY 1999 ± REVISED APRIL 2000
detailed description
reference voltage
The THS1206 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP and REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.
analog inputs
The THS1206 consists of 4 analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured as single-ended or differential inputs. The desired analog input channel can be programmed.
converter
The THS1206 uses a 12-bit pipelined multistaged architecture with 4 1-bit stages followed by 4 2-bit stages, which achieves a high sample rate with low power consumption. The THS1206 distributes the conversion over several smaller ADC sub-blocks, refining the conversion with progressively higher accuracy as the device passes the results from stage to stage. This distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input sample while the second through the eighth stages operate on the seven preceding samples.
conversion modes
The conversion can be performed in two different conversion modes. In the single conversion mode, the conversion is initiated by an external signal (CONVST). An internal oscillator controls the conversion time. In the continuous conversion mode, an external clock signal is applied to the clock input (CONV_CLK). A new conversion is started with every falling edge of the applied clock signal.
sampling rate
The maximum possible conversion rate per channel is dependent on the selected analog input channels. Table 1 shows the maximum conversion rate in the continuous conversion mode for different combinations.
Table 1. Maximum Conversion Rate in Continuous Conversion Mode
CHANNEL CONFIGURATION |
NUMBER OF |
MAXIMUM CONVERSION |
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RATE PER CHANNEL |
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1 single-ended channel |
1 |
6 MSPS |
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2 single-ended channels |
2 |
3 MSPS |
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3 single-ended channels |
3 |
2 MSPS |
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4 single-ended channels |
4 |
1.5 MSPS |
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1 differential channel |
1 |
6 MSPS |
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2 differential channels |
2 |
3 MSPS |
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1 single-ended and 1 differential channel |
2 |
3 MSPS |
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2 single-ended and 1 differential channels |
3 |
2 MSPS |
The maximum conversion rate in the continuous conversion mode per channel, fc, is given by:
fc + #6channelsMSPS
Table 2 shows the maximum conversion rate in the single conversion mode.
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
9 |
THS1206
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS217D ± MAY 1999 ± REVISED APRIL 2000
sampling rate (continued)
Table 2. Maximum Conversion Rate in Single Conversion Mode
CHANNEL CONFIGURATION |
NUMBER OF |
MAXIMUM CONVERSION |
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CHANNELS |
RATE PER CHANNEL |
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1 single-ended channel |
1 |
3 MSPS |
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2 single-ended channels |
2 |
2 MSPS |
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3 single-ended channels |
3 |
1.5 MSPS |
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4 single-ended channels |
4 |
1.2 MSPS |
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1 differential channel |
1 |
3 MSPS |
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2 differential channels |
2 |
2 MSPS |
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1 single-ended and 1 differential channel |
2 |
1.5 MSPS |
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2 single-ended and 1 differential channels |
3 |
1.2 MSPS |
single conversion mode
In single conversion mode, a single conversion of the selected analog input channels is performed. The single conversion mode is selected by setting bit 1 of control register 0 to 1.
A single conversion is initiated by pulsing the CONVST input. On the falling edge of CONVST, the sample and hold stages of the selected analog inputs are placed into hold simultaneously, and the conversion sequence for the selected channels is started.
The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. The signal DATA_AV (data available) becomes active when the trigger level is reached and indicates that the converted sample(s) is (are) written into the FIFO and can be read out. The trigger level in the single conversion mode can be selected according to Table 13.
Figure 1 shows the timing of the single conversion mode. In this mode, up to four analog input channels can be selected to be sampled simultaneously (see Table 2).
t2
CONVST
t1 |
t1 |
td(A)
AIN
Sample N
tDATA_AV
DATA_AV,
Trigger Level = 1
Figure 1. Timing of Single Conversion Mode
The time (t2) between consecutive starts of single conversions is dependent on the number of selected analog
input channels. The time tDATA_AV, until DATA_AV becomes active is given by: tDATA_AV = tpipe + n ×tc. This equation is valid for a trigger level which is equivalent to the number of selected analog input channels. For all
other trigger level conditions refer to the timing specifications of single conversion mode.
10 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
THS1206 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS217D ± MAY 1999 ± REVISED APRIL 2000
continuous conversion mode
The internal clock oscillator used in the single-conversion mode is switched off in continuous conversion mode. In continuous conversion mode, (bit 1 of control register 0 set to 0) the ADC operates with a free running external clock signal CONV_CLK. With every rising edge of the CONV_CLK signal a new converted value is written into the FIFO.
Figure 2 shows the timing of continuous conversion mode when one analog input channel is selected. The maximum throughput rate is 6 MSPS in this mode. The timing of the DATA_AV signal is shown here in the case of a trigger level set to 1 or 4.
Sample N |
Sample N+1 |
Sample N+2 |
Sample N+3 |
Sample N+4 |
Sample N+5 |
Sample N+6 |
Sample N+7 |
Sample N+8 |
Channel 1 |
Channel 1 |
Channel 1 |
Channel 1 |
Channel 1 |
Channel 1 |
Channel 1 |
Channel 1 |
Channel 1 |
AIN |
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td(A) |
td(pipe) |
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tw(CONV_CLKH) |
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tw(CONV_CLKL) |
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50% |
50% |
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CONV_CLK |
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tc |
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td(O) |
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Data Into |
Data N±5 |
Data N±4 |
Data N±3 |
Data N±2 |
Data N±1 |
Data N |
Data N+1 |
Data N+2 |
Data N+3 |
FIFO |
Channel 1 |
Channel 1 |
Channel 1 |
Channel 1 |
Channel 1 |
Channel 1 |
Channel 1 |
Channel 1 |
Channel 1 |
td(DATA_AV)
DATA_AV,
Trigger Level = 1
td(DATA_AV)
DATA_AV,
Trigger Level = 4
Figure 2. Timing of Continuous Conversion Mode (1-channel operation)
Figure 3 shows the timing of continuous conversion mode when two analog input channels are selected. The maximum throughput rate per channel is 3 MSPS in this mode. The data flow in the bottom of the figure shows the order the converted data is written into the FIFO. The timing of the DATA_AV signal shown here is for a trigger level set to 2 or 4.
Sample N |
Sample N+1 |
Sample N+2 |
Sample N+3 |
Sample N+4 |
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Channel 1,2 |
Channel 1,2 |
Channel 1,2 |
Channel 1,2 |
Channel 1,2 |
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AIN |
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td(A) |
td(Pipe) |
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tw(CONV_CLKH) |
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tw(CONV_CLKL) |
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50% |
50% |
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CONV_CLK |
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tc |
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td(O) |
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Data Into |
Data N±3 |
Data N±2 |
Data N±2 |
Data N±1 |
Data N±1 |
Data N |
Data N |
Data N+1 |
Data N+1 |
FIFO |
Channel 2 |
Channel 1 |
Channel 2 |
Channel 1 |
Channel 1 |
Channel 1 |
Channel 2 |
Channel 1 |
Channel 2 |
td(DATA_AV)
DATA_AV,
Trigger Level = 2
td(DATA_AV)
DATA_AV,
Trigger Level = 4
Figure 3. Timing of Continuous Conversion Mode (2-channel operation)
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
11 |
THS1206
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS217D ± MAY 1999 ± REVISED APRIL 2000
continuous conversion mode (continued)
Figure 4 shows the timing of continuous conversion mode when three analog input channels are selected. The maximum throughput rate per channel is 2 MSPS in this mode. The data flow in the bottom of the figure shows in which order the converted data is written into the FIFO. The timing of the DATA_AV signal shown here is for a trigger level set to 3.
Sample N |
Sample N+1 |
Sample N+2 |
Channel 1,2,3 |
Channel 1,2,3 |
Channel 1,2,3 |
AIN |
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td(A) |
td(Pipe) |
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tw(CONV_CLKH) |
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tw(CONV_CLKL) |
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50% |
50% |
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CONV_CLK |
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tc |
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td(O) |
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Data Into |
Data N±2 |
Data N±2 |
Data N±1 |
Data N±1 |
Data N±1 |
Data N |
Data N |
Data N+1 |
FIFO |
Channel 2 |
Channel 3 |
Channel 2 |
Channel 2 |
Channel 3 |
Channel 1 |
Channel 2 |
Channel 3 |
td(DATA_AV)
DATA_AV,
Trigger Level = 3
Figure 4. Timing of Continuous Conversion Mode (3-channel operation)
Figure 5 shows the timing of continuous conversion mode when four analog input channels are selected. The maximum throughput rate per channel is 1.5 MSPS in this mode. The data flow in the bottom of the figure shows in which order the converted data is written into the FIFO. The timing of the DATA_AV signal shown here is for a trigger level of 4.
Sample N |
Sample N+1 |
Sample N+2 |
Channel 1,2,3,4 |
Channel 1,2,3,4 |
Channel 1,2,3,4 |
AIN |
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td(A) |
td(Pipe) |
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tw(CONV_CLKH) |
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tw(CONV_CLKL) |
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50% |
50% |
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CONV_CLK |
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tc |
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td(O) |
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Data Into |
Data N±2 |
Data N±1 |
Data N±1 |
Data N±1 |
Data N±1 |
Data N |
Data N |
Data N |
Data N |
FIFO |
Channel 4 |
Channel 1 |
Channel 2 |
Channel 3 |
Channel 4 |
Channel 1 |
Channel 2 |
Channel 3 |
Channel 4 |
td(DATA_AV)
DATA_AV,
Trigger Level = 4
Figure 5. Timing of Continuous Conversion Mode (4-channel operation)
12 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
THS1206 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS217D ± MAY 1999 ± REVISED APRIL 2000
digital output data format
The digital output data format of the THS1206 can either be in binary format or in twos complement format. The following tables list the digital outputs for the analog input voltages.
Table 3. Binary Output Format for Single-Ended Configuration
SINGLE-ENDED, BINARY OUTPUT
ANALOG INPUT VOLTAGE |
DIGITAL OUTPUT CODE |
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AIN = VREFP |
FFFh |
AIN = (VREFP + VREFM)/2 |
800h |
AIN = VREFM |
000h |
Table 4. Two's Complement Output Format for Single-Ended Configuration
SINGLE-ENDED, TWOS COMPLEMENT
ANALOG INPUT VOLTAGE |
DIGITAL OUTPUT CODE |
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AIN = VREFP |
7FFh |
AIN = (VREFP + VREFM)/2 |
000h |
AIN = VREFM |
800h |
Table 5. Binary Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT
ANALOG INPUT VOLTAGE |
DIGITAL OUTPUT CODE |
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Vin = AINP ± AINM |
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VREF = VREFP ± VREFM |
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Vin = VREF |
FFFh |
Vin = 0 |
800h |
Vin = ±VREF |
000h |
Table 6. Two's Complement Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT
ANALOG INPUT VOLTAGE |
DIGITAL OUTPUT CODE |
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Vin = AINP ± AINM |
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VREF = VREFP ± VREFM |
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Vin = VREF |
7FFh |
Vin = 0 |
000h |
Vin = ±VREF |
800h |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
13 |