Motorola MC10H130FN, MC10H130L, MC10H130P Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Dual Latch

The MC10H130 is a MECL 10H part which is a functional/pinout duplication of the standard MECL 10K family part, with 100% improvement in clock speed and propagation delay and no increase in power±supply current.

•Propagation Delay, 1.0 ns Typical

•Power Dissipation, 155 mW Typical

•Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range)

•Voltage Compensated

•MECL 10K±Compatible

MAXIMUM RATINGS

Characteristic	Symbol	Rating	Unit
Power Supply (VCC = 0)	VEE	±8.0 to 0	Vdc
Input Voltage (VCC = 0)	VI	0 to VEE	Vdc
Output Current Ð Continuous	Iout	50	mA
Ð Surge		100
Operating Temperature Range	TA	0 to +75	°C
Storage Temperature Range Ð Plastic	Tstg	±55 to +150	°C
Ð Ceramic		±55 to +165	°C

ELECTRICAL CHARACTERISTICS (VEE = ±5.2 V ±5%) (See Note)

		0°		25°			75°
Characteristic	Symbol	Min	Max	Min	Max	Min		Max	Unit
Power Supply Current	IE	Ð	38	Ð	35	Ð		38	mA
Input Current High	IinH								μA
Pins 6, 11		Ð	468	Ð	275	Ð		275
Pins 7, 9, 10		Ð	545	Ð	320	Ð		320
Pins 4, 5, 12, 13		Ð	434	Ð	255	Ð		255
Input Current Low	IinL	0.5	Ð	0.5	Ð	0.3		Ð	μA
High Output Voltage	VOH	±1.02	±0.84	±0.98	±0.81	±0.92		±0.735	Vdc
Low Output Voltage	VOL	±1.95	±1.63	±1.95	±1.63	±1.95		±1.60	Vdc
High Input Voltage	VIH	±1.17	±0.84	±1.13	±0.81	±1.07		±0.735	Vdc
Low Input Voltage	VIL	±1.95	±1.48	±1.95	±1.48	±1.95		±1.45	Vdc
AC PARAMETERS
Propagation Delay	tpd								ns
Data		0.4	1.6	0.4	1.7	0.4		1.8
Set, Reset		0.6	1.7	0.7	1.8	0.8		1.9
Clock, CE		0.5	1.6	0.5	1.7	0.6		1.8
Rise Time	tr	0.5	1.6	0.5	1.7	0.5		1.8	ns
Fall Time	tf	0.5	1.6	0.5	1.7	0.5		1.8	ns
Set±up Time	tset	2.2	Ð	2.2	Ð	2.2		Ð	ns
Hold Time	thold	0.7	Ð	0.7	Ð	0.7		Ð	ns

NOTE:

Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated through a 50±ohm resistor to ±2.0 volts.

MC10H130

L SUFFIX

CERAMIC PACKAGE

CASE 620±10

P SUFFIX

PLASTIC PACKAGE

CASE 648±08

FN SUFFIX

PLCC

CASE 775±02

LOGIC DIAGRAM

	S1				5												2
	D1				7									Q1
	CE1				6												3
														Q1
	R1				4										VCC1 = PIN 1
	C				9										VCC2 = PIN 16
	R2			13											VEE = PIN 8
																	14
														Q2
CE2 11
	D2			10										Q2			15
	S2			12

TRUTH TABLE

D	C	CE	Qn+1
L	L	L	L
H	L	L	H
X	L	H	Qn
X	H	L	Qn
X	H	H	Qn

DIP

PIN ASSIGNMENT

VCC1						1		16			VCC2
						2		15
		Q1									Q2
						3		14
		Q1									Q2
		R1				4		13			R2
		S1				5		12			S2
						6		11
	CE1										CE2
						7		10
		D1									D2
						8		9
VEE											C

Pin assignment is for Dual±in±Line Package.

For PLCC pin assignment, see the Pin Conversion

Tables on page 6±11 of the Motorola MECL Data

Book (DL122/D).

3/93

Motorola, Inc. 1996

2±49

REV 5

MC10H130

APPLICATION INFORMATION

The MC10H130 is a clocked dual D type latch. Each latch may be clocked separately by holding the common clock in the low state, and using the clock enable inputs for the clocking function. If the common clock is to be used to clock the latch, the clock enable (CE) inputs must be in the low state. In this mode, the enable inputs perform the function of controlling the common clock (C).

Any change at the D input will be reflected at the output

while the clock is low. The outputs are latched on the positive transition of the clock. While the clock is in the high state, a change in the information present at the data inputs will not affect the output information.

The set and reset inputs do not override the clock and D inputs. They are effective only when either C or CE or both are high.

MOTOROLA	2±50	MECL Data
		DL122 Ð Rev 6