Fairchild Semiconductor 74ACT652SPC, 74ACT652SCX, 74ACT652SC, 74ACT652MTCX, 74ACT652MTC Datasheet

0 (0)

August 1999

Revised September 2000

74ACT652

Transceiver/Register

General Description

The ACT652 consists of bus transceiver circuits with D- type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to the HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function.

Features

Independent registers for A and B buses

Multiplexed real-time and stored data

Outputs source/sink 24 mA

TTL-compatible inputs

Ordering Code:

Order Number

Package Number

Package Description

 

 

 

74ACT652SC

M24B

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

 

 

 

74ACT652MTC

MTC24

24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

 

 

 

74ACT652SPC

N24C

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

 

 

 

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

 

Pin Descriptions

Pin Names

Description

 

 

A0–A7, B0–B7

A and B Inputs/3-STATE Outputs

CPAB, CPBA

Clock Inputs

SAB, SBA

Select Inputs

 

 

OEAB,

OEBA

 

Output Enable Inputs

 

 

 

 

FACT is a trademark of Fairchild Semiconductor Corporation.

Transceiver/Register 74ACT652

© 2000 Fairchild Semiconductor Corporation

DS500310

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74ACT652

Function Table

 

 

 

 

 

Inputs

 

 

Inputs/Outputs (Note 1)

Operating Mode

 

 

 

 

 

 

 

 

 

 

 

 

OEAB

 

OEBA

CPAB

CPBA

SAB

SBA

A0 thru A7

B0 thru B7

 

 

L

 

H

H or L

H or L

X

X

Input

Input

Isolation

 

 

 

 

 

 

 

 

 

 

 

 

L

 

H

 

 

X

X

 

 

Store A and B Data

 

 

 

 

 

 

 

 

 

 

 

 

X

 

H

 

H or L

X

X

Input

Not Specified

Store A, Hold B

 

 

 

 

 

 

 

 

 

 

 

 

H

 

H

 

 

X

X

Input

Output

Store A in Both Registers

 

 

 

 

 

 

 

 

 

 

 

 

L

 

X

H or L

 

X

X

Not Specified

Input

Hold A, Store B

 

 

 

 

 

 

 

 

 

 

 

 

L

 

L

 

 

X

X

Output

Input

Store B in Both Registers

 

 

 

 

 

 

 

 

 

 

 

 

L

 

L

X

X

X

L

Output

Input

Real-Time B Data to A Bus

 

 

 

 

 

 

 

 

 

 

 

 

L

 

L

X

H or L

X

H

 

 

Store B Data to A Bus

 

 

 

 

 

 

 

 

 

 

 

 

H

 

H

X

X

L

X

Input

Output

Real-Time A Data to B Bus

 

 

 

 

 

 

 

 

 

 

 

 

H

 

H

H or L

X

H

X

 

 

Stored A Data to B Bus

 

 

 

 

 

 

 

 

 

 

 

 

H

 

L

H or L

H or L

H

H

Output

Output

Stored A Data to B Bus and

 

 

 

 

 

 

 

 

 

 

 

Stored B Data to A Bus

 

 

 

 

 

 

 

 

 

 

H = HIGH Voltage Level

 

 

 

 

 

 

 

L = LOW Voltage Level

 

 

 

 

 

 

 

X = Immaterial

 

 

 

 

 

 

 

 

 

= LOW-to-HIGH Clock Transition

 

 

 

 

 

 

Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Fairchild Semiconductor 74ACT652SPC, 74ACT652SCX, 74ACT652SC, 74ACT652MTCX, 74ACT652MTC Datasheet

Functional Description

In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both.

The select (SAB, SBA) controls can multiplex stored and real-time.

The examples in Figure 1 demonstrate the four fundamental bus-management functions that can be performed with the Octal bus transceivers and receivers.

Note A: Real-Time

Transfer Bus B to Bus A

OEAB

OEBA

CPAB

CPBA

SAB

SBA

L

L

X

X

X

L

Note C: Storage

Data on the A or B data bus, or both can be stored in the internal D-type flip-flop by LOW to HIGH transitions at the appropriate Clock Inputs (CPAB, CPBA) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state.

Note B: Real-Time

Transfer Bus A to Bus B

OEAB

OEBA

CPAB

CPBA

SAB

SBA

H

H

X

X

L

X

Note D: Transfer Storage

Data to A or B

OEAB

OEBA

CPAB

CPBA

SAB

SBA

OEAB

OEBA

CPAB CPBA

SAB

SBA

X

H

X

X

X

H

L

H or L H or L

H

H

L

X

X

 

X

X

 

 

 

 

 

L

H

 

 

X

X

 

 

 

 

 

 

 

 

 

 

 

FIGURE 1.

 

 

 

 

74ACT652

3

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