Fairchild Semiconductor 74ACT574SJX, 74ACT574SJ, 74ACT574SCX, 74ACT574SC, 74ACT574PC Datasheet

September 1988

Revised November 1999

74AC574 • 74ACT574

Octal D-Type Flip-Flop with 3-STATE Outputs

General Description

The AC/ACT574 is a high-speed, low power octal flip-flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D-type inputs is stored in the flip-flops on the LOW-to-HIGH Clock (CP) transition.

The AC/ACT574 is functionally identical to the AC/ACT374 except for the pinouts.

Features

■ICC and IOZ reduced by 50%

■Inputs and outputs on opposite sides of package allowing easy interface with microprocessors

■Useful as input or output port for microprocessors

■Functionally identical to AC/ACT374

■3-STATE outputs for bus-oriented applications

■Outputs source/sink 24 mA

■ACT574 has TTL-compatible inputs

Ordering Code:

Order Number	Package Number	Package Description
74AC574SC	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74AC574SJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC574MTC	MTC20	20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC574PC	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT574SC	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-01
74ACT574SJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT574MTC	MTC20	20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT574PC	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

	Pin Names		Description
	D0–D7		Data Inputs
	CP		Clock Pulse Input
			3-STATE Output Enable Input
	OE
	O0–O7		3-STATE Outputs

FACT is a trademark of Fairchild Semiconductor Corporation.

Outputs STATE-3 with Flop-Flip Type-D Octal 74ACT574 • 74AC574

© 1999 Fairchild Semiconductor Corporation

DS009910

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74AC574 • 74ACT574

Functional Description

The AC/ACT574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops.

Logic Diagram

Function Table

	Inputs			Internal	Outputs	Function
	OE	CP D		Q	ON
	H	H	L	NC	Z	Hold
	H	H	H	NC	Z	Hold
	H	L		L	Z	Load
	H	H		H	Z	Load
	L	L		L	L	Data Available
	L	H		H	H	Data Available
	L	H	L	NC	NC	No Change in Data
	L	H	H	NC	NC	No Change in Data

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

= LOW-to-HIGH Transition

NC = No Change

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings(Note 1)

Supply Voltage (VCC)		− 0.5V to + 7.0V
DC Input Diode Current (IIK)
VI =	− 0.5V	− 20 mA
VI =	VCC + 0.5V	+ 20 mA
DC Input Voltage (VI)		− 0.5V to VCC + 0.5V
DC Output Diode Current (IOK)
VO =	− 0.5V	− 20 mA
VO =	VCC + 0.5V	+ 20 mA
DC Output Voltage (VO)		− 0.5V to VCC + 0.5V
DC Output Source
or Sink Current (IO)		± 50 mA
DC VCC or Ground Current
Per Output Pin (ICC or IGND)		± 50 mA
Storage Temperature (TSTG)		− 65° C to + 150° C
Junction Temperature (TJ)
PDIP		140° C

Recommended Operating

Conditions

Supply Voltage (VCC)
AC	2.0V to 6.0V
ACT	4.5V to 5.5V
Input Voltage (VI)	0V to VCC
Output Voltage (VO)	0V to VCC
Operating Temperature (TA)	− 40° C to + 85° C
Minimum Input Edge Rate (∆ V/∆ t)
AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V	125 mV/ns
Minimum Input Edge Rate (∆ V/∆ t)
ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V	125 mV/ns

Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.

DC Electrical Characteristics for AC

Symbol	Parameter	VCC	TA = 25° C		TA = − 40° C to + 85° C	Units		Conditions
		(V)	Typ	Guaranteed Limits
VIH	Minimum HIGH Level	3.0	1.5	2.1	2.1		VOUT =		0.1V
	Input Voltage	4.5	2.25	3.15	3.15	V	or VCC −			0.1V
		5.5	2.75	3.85	3.85
VIL	Maximum LOW Level	3.0	1.5	0.9	0.9		VOUT =		0.1V
	Input Voltage	4.5	2.25	1.35	1.35	V	or VCC −			0.1V
		5.5	2.75	1.65	1.65
VOH	Minimum HIGH Level	3.0	2.99	2.9	2.9
	Output Voltage	4.5	4.49	4.4	4.4	V	IOUT =		−	50 µ A
		5.5	5.49	5.4	5.4
		3.0		2.56	2.46		VIN =	VIL or VIH
		4.5		3.86	3.76	V	IOH =	−	12 mA
		5.5		4.86	4.76		IOH =	− 24 mA IOH
							IOH =	− 24 mA (Note 2)
VOL	Maximum LOW Level	3.0	0.002	0.1	0.1
	Output Voltage	4.5	0.001	0.1	0.1	V	IOUT =		50 µ A
		5.5	0.001	0.1	0.1
							VIN =	VILor VIH
		3.0		0.36	0.44		IOL =	12 mA
		4.5		0.36	0.44	V	IOL =	24 mA
		5.5		0.36	0.44		IOL =	24 mA (Note 2)
IIN (Note 4)	Maximum Input Leakage Current	5.5		± 0.1	± 1.0	µ A	VI =	VCC, GND
IOZ	Maximum						VI (OE) = VIL, VIH
	3-STATE	5.5		± 0.25	± 2.5	µ A	VI =	VCC, VGND
	Leakage Current						VO =	VCC, GND
IOLD	Minimum Dynamic	5.5			75	mA	VOLD =		1.65V
IOHD	Output Current (Note 3)	5.5			− 75	mA	VOHD =			3.85V
ICC (Note 4)	Maximum Quiescent Supply Current	5.5		4.0	40.0	µ A	VIN =	VCC or GND

Note 2: All outputs loaded; thresholds on input associated with output under test.

Note 3: Maximum test duration 2.0 ms, one output loaded at a time.

Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.

74ACT574 • 74AC574

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