Fairchild Semiconductor 74ACT534SJX, 74ACT534SJ, 74ACT534SCX, 74ACT534SC, 74ACT534PC Datasheet

November 1988

Revised November 1999

74ACT534

Octal D-Type Flip-Flop with 3-STATE Outputs

General Description

The ACT534 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flipflops. The ACT534 is the same as the ACT374 except that the outputs are inverted.

Features

■ICC and IOZ reduced by 50%

■Edge-triggered D-type inputs

■Buffered positive edge-triggered clock

■3-STATE outputs for bus-oriented applications

■Outputs source/sink 24 mA

■ACT534 has TTL-compatible inputs

■Inverted output version of ACT374

Ordering Code:

Order Number	Package Number	Package Description
74ACT534SC	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACT534SJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT534PC	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

	Pin Names					Description
	D0–D7					Data Inputs
	CP					Clock Pulse Input
						3-STATE Output Enable Input
	OE
	O	0–O			7	Complementary 3-STATE Outputs

FACT is a trademark of Fairchild Semiconductor Corporation.

Outputs STATE-3 with Flop-Flip Type-D Octal 74ACT534

© 1999 Fairchild Semiconductor Corporation

DS009965

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74ACT534

Functional Description

The ACT534 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE complementary outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP)

transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.

Function Table

	Inputs		Output
CP	OE	D		O
	L	H		L
	L	L		H
L	L	X
				O	0
X	H	X		Z

H = HIGH Voltage Level

L = LOW Voltage Level X = Immaterial

= LOW-to-HIGH Clock Transition Z = High Impedance

O0 = Value stored from previous clock cycle

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings(Note 1)

Supply Voltage (V )		− 0.5V to + 7.0V
	CC
DC Input Diode Current (IIK)
VI =	− 0.5V	− 20 mA
VI =	VCC + 0.5V	+ 20 mA
DC Input Voltage (VI)		− 0.5V to VCC + 0.5V
DC Output Diode Current (IOK)
VO =	− 0.5V	− 20 mA
VO =	VCC + 0.5V	+ 20 mA
DC Output Voltage (VO)		− 0.5V to VCC + 0.5V
DC Output Source
or Sink Current (IO)		± 50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND)		± 50 mA
Storage Temperature (TSTG)		− 65° C to + 150° C
Junction Temperature (TJ)
PDIP		140° C

Recommended Operating

Conditions

Supply Voltage (V		)	4.5V to 5.5V
	CC
Input Voltage (VI)			0V to VCC
Output Voltage (VO)			0V to VCC
Operating Temperature (TA)			− 40° C to + 85° C
Minimum Input Edge Rate (∆ V/∆ t)
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V			125 mV/ns

Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.

DC Electrical Characteristics

Symbol	Parameter	VCC	TA = + 25° C		TA = − 40° C to + 85° C	Units		Conditions
		(V)	Typ	Guaranteed Limits
VIH	Minimum HIGH Level	4.5	1.5	2.0	2.0	V	VOUT =		0.1V
	Input Voltage	5.5	1.5	2.0	2.0		or VCC −			0.1V
VIL	Maximum LOW Level	4.5	1.5	0.8	0.8	V	VOUT =		0.1V
	Input Voltage	5.5	1.5	0.8	0.8		or VCC −			0.1V
VOH	Minimum HIGH Level	4.5	4.49	4.4	4.4	V	IOUT =		−	50 µ A
	Output Voltage	5.5	5.49	5.4	5.4
							VIN =	VIL or VIH
		4.5		3.86	3.76	V	IOH =	−	24 mA
		5.5		4.86	4.76		IOH =	− 24 mA (Note 2)
VOL	Maximum LOW Level	4.5	0.001	0.1	0.1	V	IOUT =		50 µ A
	Output Voltage	5.5	0.001	0.1	0.1
							VIN =	VIL or VIH
		4.5		0.36	0.44	V	IOL =	24 mA
		5.5		0.36	0.44		IOL =	24 mA (Note 2)
IIN	Maximum Input	5.5		± 0.1	± 1.0	µ A	VI =	VCC, GND
	Leakage Current
IOZ	Maximum 3-STATE	5.5		± 0.25	± 2.5	µ A	VI =	VIL, VIH
	Current						VO =	VCC, GND
ICCT	Maximum	5.5	0.6		1.5	mA	VI =	VCC − 2.1V
	ICC/Input
IOLD	Minimum Dynamic	5.5			75	mA	VOLD =		1.65V Max
IOHD	Output Current (Note 3)	5.5			− 75	mA	VOHD =			3.85V Min
ICC	Maximum Quiescent	5.5		4.0	40.0	µ A	VIN =	VCC
	Supply Current						or GND

Note 2: All outputs loaded; thresholds on input associated with output under test.

Note 3: Maximum test duration 2.0 ms, one output loaded at a time.

74ACT534

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