Fairchild Semiconductor 74ACT821SPC, 74ACT821SCX, 74ACT821SC, 74ACT821MTCX, 74ACT821MTC Datasheet
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November 1988
Revised August 2000
74AC821 • 74ACT821
10-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description |
Features |
The AC/ACT821 is a 10-bit D-type flip-flop with 3-STATE |
■ 3-STATE outputs for bus interfacing |
outputs arranged in a broadside pinout. |
■ Noninverting outputs |
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■ Outputs source/sink 24 mA |
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■ TTL compatible inputs |
Ordering Code:
Order Number |
Package Number |
Package Description |
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74AC821SC |
M24B |
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide |
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74AC821SPC |
N24C |
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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74ACT821SC |
M24B |
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide |
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74ACT821MTC |
MTC24 |
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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74ACT821SPC |
N24C |
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (SPC not available in Tapeand Reel.)
Logic Symbols |
Connection Diagram |
IEEE/IEC
Pin Descriptions
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Pin Names |
Description |
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D0–D9 |
Data Inputs |
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O0–O9 |
Data Outputs |
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Output Enable Input |
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OE |
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CP |
Clock Input |
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FACT is a trademark of Fairchild Semiconductor Corporation.
Outputs STATE-3 with Flop-Flip Type-D Bit-10 74ACT821 • 74AC821
© 2000 Fairchild Semiconductor Corporation |
DS010139 |
www.fairchildsemi.com |
74AC821 • 74ACT821
Functional Description
The AC/ACT821 consists of ten D-type edge-triggered flip- |
With OE LOW the contents of the flip-flops are available at |
flops. The buffered Clock (CP) and buffered Output Enable |
the outputs. When OE is HIGH the outputs go to the high |
(OE) are common to all flip-flops. The flip-flops will store |
impedance state. Operation of the OE input does not affect |
the state of their individual D inputs that meet the setup and |
the state of the flip-flops. |
hold time requirements on the LOW-to-HIGH CP transition. |
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Function Table
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Inputs |
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Internal |
Outputs |
Function |
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OE |
CP |
D |
Q |
O |
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H |
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L |
L |
Z |
High Z |
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H |
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H |
H |
Z |
High Z |
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L |
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L |
L |
L |
Load |
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L |
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H |
H |
H |
Load |
H = HIGH Voltage Level
L = LOW Voltage Level
Z = HIGH Impedance
= LOW-to-HIGH Clock Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
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− 0.5V to + 7.0V |
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DC Input Diode Current (IIK) |
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VI = |
− 0.5V |
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− |
20 mA |
VI = |
VCC + 0.5V |
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+ |
20 mA |
DC Input Voltage (VI) |
− |
0.5V to VCC + 0.5V |
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DC Output Diode Current (IOK) |
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VO = |
− 0.5V |
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− |
20 mA |
VO = |
VCC + 0.5V |
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+ |
20 mA |
DC Output Voltage (VO) |
− |
0.5V to VCC + 0.5V |
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DC Output Source |
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or Sink Current (IO) |
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± |
50 mA |
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DC VCC or Ground Current |
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per Output Pin (ICC or IGND) |
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± |
50 mA |
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Storage Temperature (TSTG) |
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− 65° C to + |
150° C |
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Junction Temperature (TJ) |
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PDIP |
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140° C |
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Recommended Operating
Conditions
Supply Voltage (VCC) |
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AC |
2.0V to 6.0V |
ACT |
4.5V to 5.5V |
Input Voltage (VI) |
0V to VCC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
− 40° C to + 85° C |
Minimum Input Edge Rate (∆ V/∆ t) |
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AC Devices |
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VIN from 30% to 70% of VCC |
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VCC @ 3.3V, 4.5V, 5.5V |
125 mV/ns |
Minimum Input Edge Rate (∆ V/∆ t) |
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ACT Devices |
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VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
125 mV/ns |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol |
Parameter |
VCC |
TA = + 25° C |
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TA = − 40° C to + 85° C |
Units |
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Conditions |
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(V) |
Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH Level |
3.0 |
1.5 |
2.1 |
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2.1 |
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VOUT = |
0.1V |
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Input Voltage |
4.5 |
2.25 |
3.15 |
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3.15 |
V |
or VCC − |
0.1V |
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5.5 |
2.75 |
3.85 |
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3.85 |
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VIL |
Maximum LOW Level |
3.0 |
1.5 |
0.9 |
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0.9 |
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VOUT = |
0.1V |
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Input Voltage |
4.5 |
2.25 |
1.35 |
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1.35 |
V |
or VCC − |
0.1V |
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5.5 |
2.75 |
1.65 |
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1.65 |
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VOH |
Minimum HIGH Level |
3.0 |
2.99 |
2.9 |
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2.9 |
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Output Voltage |
4.5 |
4.49 |
4.4 |
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4.4 |
V |
IOUT = |
− |
50 µ A |
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5.5 |
5.49 |
5.4 |
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5.4 |
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VIN = |
VIL or VIH |
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3.0 |
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2.56 |
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2.46 |
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IOH = |
− |
12 mA |
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4.5 |
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3.86 |
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3.76 |
V |
IOH = |
− |
24 mA |
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5.5 |
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4.86 |
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4.76 |
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IOH = |
− |
24 mA (Note 2) |
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VOL |
Maximum LOW Level |
3.0 |
0.002 |
0.1 |
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0.1 |
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Output Voltage |
4.5 |
0.001 |
0.1 |
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0.1 |
V |
IOUT = |
50 µ A |
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5.5 |
0.001 |
0.1 |
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0.1 |
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VIN = |
VIL or VIH |
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3.0 |
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0.36 |
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0.44 |
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IOL = |
12 mA |
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4.5 |
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0.36 |
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0.44 |
V |
IOL = |
24 mA |
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5.5 |
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0.36 |
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0.44 |
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IOL = |
24 mA (Note 2) |
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IIN (Note 4) |
Maximum Input Leakage Current |
5.5 |
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± 0.1 |
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± 1.0 |
µ A |
VI = |
VCC, GND |
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IOZ |
Maximum 3-STATE Current |
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VI (OE) = |
VIL, VIH |
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5.5 |
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± 0.5 |
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± 5.0 |
µ A |
VI = |
VCC, GND |
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VO = |
VCC, GND |
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IOLD |
Minimum Dynamic |
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5.5 |
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75 |
mA |
VOLD = |
1.65V Max |
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IOHD |
Output Current (Note 3) |
5.5 |
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− 75 |
mA |
VOHD = |
3.85V Min |
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ICC (Note 4) |
Maximum Quiescent Supply Current |
5.5 |
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8.0 |
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80.0 |
µ A |
VIN = |
VCC or GND |
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Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
74ACT821 • 74AC821
3 |
www.fairchildsemi.com |
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