Fairchild Semiconductor 74ACT715SCX, 74ACT715SC, 74ACT715RSCX, 74ACT715RSC, 74ACT715RPC Datasheet

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November 1988 Revised December 1998

74ACT715•74ACT715-R Programmable Video Sync Generator

General Description

The ACT715 and ACT715-R are 20-pin TTL-input compatible devices capable of generating Horizontal, Vertical and Composite Sync and Blank signals for televisions and monitors. All pulse widths are completely definable by the user. The devices are capable of generating signals for both interlaced and noninterlaced modes of operation. Equalization and serra tion pulses can be introduced into the Composite Sync signal when needed.

Four additional signals can also be made available when Composite Sync or Bl ank are used. These sign als can be used to generate horizontal or vertical gating pulses, cursor position or vertical Interrupt signal.

These devices make no assumptions concernin g the system architecture. Line rate and field/frame rate are all a function of the values programme d into the data registers, the status register, and the input clock frequency.

The ACT715 is mask pr ogrammed to default to a Clock Disable state. Bit 10 of the Status Register, Register 0,

defaults to a logic “0”. This facilitates (re)programming before operation.

The ACT715-R is the same as th e ACT715 in all respects except that the ACT715-R is m ask programmed to default

to a Clock Enabled state. Bit 10 of the Status Register defaults to a logic “1”. Although completely (re)programmable, the ACT715-R version is be tter suite d for application s using the default 14.31818 MHz RS-170 register values. This feature allows power-up directly into operati on, following a single CLEAR pulse.

Features

■ Maximum Input Clock Frequency > 130 MHz ■ Interlaced and non-interlaced formats available ■ Separate or compo site horizontal and vertical Sync and

Blank signals available

■ Complete control of pulse width via register

programming

■ All inputs are TTL compatible ■ 8 mA drive on all outputs ■ Default RS170/NTSC values mask programmed into

registers

■ ACT715-R is mask programm ed to default to a Clock

Enable state for easier start-up into 14.31818 MHz RS170 timing

Ordering Code:

Device also available in Tape and Reel. Specify by appendin g s uf f ix let t er “X” to the ordering co de.

Connection Diagram

Pin Assignment for DIP and SOIC

FACT is a tra demark of Fairchild Semico nductor Corporat ion.

Order Number Package Number Package Description

74ACT715SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 74ACT715PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACT715-RSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 74ACT715-RPC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

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74ACT715•74ACT715-R

Logic Block Diagram

Pin Description

There are a Total of 13 inputs and 5 outputs on the ACT715.

Data Inputs D0–D7: The Data Inp ut pins connect to the Address Register and the Data Input Register.

ADDR

/DATA: The ADDR/DATA signal is l atched into the

device on the falling edge of the LOAD signal. The sign al determines if an address (0) or data (1) is present on the data bus.

/HBYTE: The L/HBYTE signal is latched into the device

on the falling edge of the LOAD signal. The signal determines if data will be read into the 8 LSB’s (0) or the 4 MSB’s (1) of the Data Registers. A 1 on this pin when an ADDR/DATA is a 0 enables Auto-Load Mode.

LOAD: The LOAD control pin lo ads data into the Address or Data Registers on the rising edge. AD DR

/DATA and L/ HBYTE data is loaded into the device on the falling edge of the LOAD. The LOAD pin has been implemented as a Schmitt trigger input for better noise immunity.

CLOCK: System CLOCK input from which all timing is derived. The clock pin ha s be en i mp leme nte d a s a S chm i tt trigger for better noise immunity. The CLOCK and the LOAD signal are asynch ronous and independent. Outp ut state changes occur on the falling edge of CLOCK.

CLR: The CLEAR pin is an asyn chrono us inp ut that init ializes the device when it is HIGH. Initialization consists of setting all registe rs to their mask programme d values, and

initializing all counters, comparators and registers. The CLEAR pin has been impleme nted as a Schmitt tr igger for better noise immunity. A CLEAR pulse should be ass er ted by the user immediately after power-u p to ensure proper

initialization of the registers—even if the user plans to (re)program the device.

Note: A CLEAR p ulse will disable the CLO CK on the ACT715 and will enable the CLOCK on th e ACT715-R.

ODD/EVEN: Output that identifies if display is in odd (HIGH) or even (LOW) field of interlace whe n device is in interlaced mode of operation. In noninterlaced mode of operation this output is a lways HIGH. Data can be seria lly scanned out on this pin during Scan Mode.

VCSYNC: Outputs Vertical or Composite Sync signal based on value of the Status Register. Equalization a nd Serration pulses will (if enabled) be output on the VCSYNC signal in composite mode only.

VCBLANK: Outputs Vertical or Composite Blanking signal based on value of the Status Register.

HBLHDR: Outputs Horizontal Blanking signal, Horizonta l Gating signal or Cursor Position based on value of the Status Register.

HSYNVDR: Outputs Hori zontal Sync signal, Vertical Gating signal or Vertical Interrupt signal based on value of Status Register.

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74ACT715•74ACT715-R

All of the data registers are 12 bits wide. Width’s of all pulses are defined by specifying the star t count and end count of all pulses. Horizont al pulses are specified withrespect-to the number o f clock pulses per lin e and ver tical pulses are specified with-respect-to the number of lines per frame.

REG0—STATUS REGISTER

The Status Register con trols the mode of operation, the signals that are output and the polarity of these outputs. The default value for the Status Registe r is 0 ( 000 Hex) for

the ACT715 and is “1024” (400 Hex) for the ACT715-R.

Bits 0–2

Bits 3–4

Double Equalization and Serration mode will output equ alization and serration puls es at twi ce th e HS YNC fre que ncy (i.e., 2 equalization or serration pulses for every HSYNC pulse). Single Equalization and Serration mode will output an equalization or serra tion pulse for every HSYNC pulse. In Interlaced mode equalization and serration pulses will be output during th e VBLANK period of every odd and even field. Interlaced Single Equaliz ation an d Serrat ion mode is not possible with this part.

Bits 5–8

Bits 5 through 8 con trol the po larit y of the ou tputs. A value of zero in these bit locations indicates an output pulse active LOW. A value of 1 indicates an active HIGH pulse.

B5— VCBLANK Polarity B6— VCSYNC Polarity B7— HBLHDR Polarity B8— HSYNVDR Polarity

Bits 9–11

Bits 9 through 11 enable several different features of the device.

B9— Enable Equalization/Serration Pulses (0)

Disable Equalization/Serration Pulses (1)

B10— Disable System Clock (0)

Enable System Clock (1) Default values for B10 are “0” in the ACT715

and “1” in the ACT715-R.

B11— Disable Counter T est Mode (0)

Enable Counter Test Mode (1) This bit is not intended for the user but is for

internal testing only.

HORIZONTAL INTERVAL REGISTERS

The Horizontal Inter val Registers deter mine the number of clock cycles per line and the characteristics of the Horizontal Sync and Blank pulses.

REG1— Horizontal Front Porch REG2— Horizontal Sync Pulse End Time REG3— Horizontal Blanking Width REG4— Horizontal Interval Width # of Clocks

per Line

VERTICAL INTERVAL REGISTERS

The Vertical Interval Re gisters determine the number of lines per f r am e, an d t he ch aracteristics o f t he Vertical B la nk and Sync Pulses.

REG5— Vertical Front Porch REG6— Vertical Sync Pulse End Time REG7— Vertical Blanking Width REG8— Vertical Interval Width # of Lines

per Frame

EQUALIZATION AND SERRATION PULSE SPECIFICATION REGISTERS

These registers determine the width of equalization and serration pulses an d the vertical interval over w hich they occur.

REG 9— Equalization Pulse Width End Time REG10— Serration Pulse Width End Time REG11— Equalization/Serration Pulse Vertical

Interval Start Time

REG12— Equalization/Serration Pulse Vertical

Interval End Time

VERTICAL INTERRUPT SPECIFICATION REGISTERS

These Registers dete rmine the width of the Vertical Interrupt signal if used.

REG13— Vertical Interrupt Activate Time REG14— Vertical Interrupt Deactivate Time

CURSOR LOCATION REGISTERS

These 4 registers determine the cursor position location, or they generate separate Horizontal an d Vertical Gati ng signals.

REG15— Horizontal Cursor Position Start Time REG16— Horizontal Cursor Position End Time REG17— Vertical Cursor Position Start Time REG18— Vertical Cursor Position End Time

2 B1 B0

VCBLANK VCSYNC HBLHDR HSYNVDR

0 0 0 CBLANK CSYNC HGATE VGATE

(DEFAULT)

0 0 1 VBLANK CSYNC HBLANK VGATE 0 1 0 CBLANK VSYNC HGATE HSYNC 0 1 1 VBLANK VSYNC HBLANK HSYNC 1 0 0 CBLANK CSYNC CUSOR VINT 1 0 1 VBLANK CSYNC HBLANK VINT 1 1 0 CBLANK VSYNC CUSOR HSYNC 1 1 1 VBLANK VSYNC HBLANK HSYNC

4B3

Mode of Operation

0 0 Interlaced Double Serration and

(DEFAULT)

Equalization

0 1 Non Interlaced Double Serration 1 0 Illegal State 1 1 Non Interlaced Single Serration and Equalization

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74ACT715•74ACT715-R

Signal Specification

HORIZONTAL SYNC AND BLANK SPECIFICATIONS

All horizontal si gnals are define d by a star t and end time. The start and end times are specified in number of clock cycles per line. The start of the horizontal line is considered pulse 1 not 0. A ll values of the horizont al timing registers are referenced to the falling edge of the Hori zontal Blank signal (see Figure 1). Since the first CLOCK edge, CLOCK #1, causes the first falling edge of the Horizontal Blank re f-

erence pulse, edges referenced to this first Horizontal edge are n + 1 CLOCKs away, where “n” is the width of the tim-

ing in question. Registers 1, 2, an d 3 are programmed in this manner. The horizontal counters start at 1 and count until HMAX. The value of HMAX must be divisible by 2. This limitation is imposed beca use durin g interlace operation this value is internally divided by 2 in order to generate serration and equalizati on pulses at 2 × the horizontal frequency. Horizontal signals will change on the falling edge of the CLOCK signal. Signal specifications are shown below.

FIGURE 1. Horizontal Waveform Specificatio n

Horizontal Period (HPER) = REG(4) × ckper Horizontal Blanking Width: = [REG(3) − 1] × ckper Horizontal Sync Width: = [REG(2) − REG(1)] × ckper Horizontal Front Porch: = [REG(1) − 1] × ckper

VERTICAL SYNC AND BLANK SPECIFICATION

All vertical sig nals are defi ned in ter ms of numbe r of lines per frame. This is tr ue i n bo th interlaced and non inte r l ace d modes of operation. Care must be taken to not s pecify the Vertical Registers in term s of lines p er field. Sin ce the fir st CLOCK edge, CLOCK #1, causes the first falling edge of the Vertical Blank (first Hor izontal Blank) reference pulse, edges referenced to this fir st edge are n + 1 line s away, where “n” is the width of the timing in question. Registers 5, 6, and 7 are pr ogramm ed i n th is m an ner. Also, in the in ter laced mode, vertical timing is based on half-lines. Therefore registers 5, 6, and 7 must contain a value twice the total horizontal (odd and even) plus 1 (as described above). In non-interlaced mode, all vertical timing is based on whole-lines. Register 8 is always based on whole-lines and does not add 1 for the fi rst clock. The vertica l counte r starts at the value of 1 and counts until the value of VMAX. No restrictions exist o n the values placed in the vertical registers. Vertical Blank will change on the leading edge of HBLANK. Vertical Sync will change on the leading edge of HSYNC. (See Figure 2.) Vertical Frame Period (VPER) = REG(8) × hper

Vertical Field Period (VPER/n) = REG(8) × hper/n Vertical Blanking Width = [REG(7) − 1] × hper/n

Vertical Syncing Width = [REG(6) − REG(5)] × hper/n Vertical Front Porch = [REG(5) − 1] × hper/n where n = 1 for noninterlaced n = 2 for int erlaced

COMPOSITE SYNC AND BLANK SPECIFICATION

Composite Sync and Bl ank sign al s are cr eat ed by lo gica lly ANDing (ORing) the active LOW (HIG H) sig nal s o f th e co rresponding vertical and horizontal components of these signals. The Composite Sync signal may also inclu de serration and/or equalization pulses. The Serration pulse interval occurs in place of the Vertical Sync interval. Equalization pulses occur preceding and/or following the Serration pulses. The width and location of these p ulses can be programmed throug h the registers shown below. (See Figure 3.)

Horizontal Equalization PW = [REG(9) − REG(1)] × ckper REG 9 = (HFP) + (HEQP) + 1 Horizontal Serration PW: = [REG(4)/n + REG(1) −

REG(10)] × ckper REG 10 = (HFP) + (HPER/2) − (HSERR) + 1

Where n = 1 for nonint erlaced s ingle serra tion/equ al-

ization

n = 2 for noninterlaced double serration/equal-

ization

n = 2 for interlaced operation

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74ACT715•74ACT715-R

FIGURE 2. Vertical Waveform Specification

FIGURE 3. Equalization/Serration Interval Programming

HORIZONTAL AND VERTICAL GATING SIGNALS

Horizontal Drive and Vertical Drive outputs can be ut ilized as general purpo se Gati n g S ign al s. Hor i zont al and Vertical Gating Signals are available for use when Co mp osi te Sync and Blank signals are selected and the value of Bit 2 of the Status Register is 0. The Vertical Gating signal will change in the same manner as that specified for the Vertical Blank.

Horizontal Gating Signal Width = [REG(16) − REG(15)] ×

ckper

Vertical Gating Si gnal Width: = [REG(18) − REG(17)] ×

hper

CURSOR POSITION AND VERTICAL INTERRUPT

The Cursor Position and Vertical Interrupt si gnal are available when Composite Sync an d B lank signals are selected and Bit 2 of the Status Register is set to the value of 1. The Cursor Position generates a single pulse of n clocks wide during every line that the cursor is specified. The signals are generated by logically ORing (ANDing) the active LOW (HIGH) signals specified by the regist ers used for generating Horizontal and Vertical Gating signals. The Vertical Interrupt signal generates a pulse du ring th e verti cal int erval specified. The Vertical Interrupt signal will change in the same manner as that specified for the Vertical Blanking signal.

Horizontal Cursor Width = [R EG(16) − REG(15)] × ckper Vertical Cursor Width = [REG(18) − REG(17)] × hper Vertical Interrupt Width = [REG(14) − REG(13)] × hper

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