Fairchild Semiconductor 74ACT573SJX, 74ACT573SCX, 74ACT573SC, 74ACT573PC, 74ACT573MTCX Datasheet

November 1988

Revised October 1999

74AC573 • 74ACT573

Octal Latch with 3-STATE Outputs

General Description

The 74AC573 and 74ACT573 are high-speed octal latches with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs.

The 74AC573 and 74ACT573 are functionally identical to the 74AC373 and 74ACT373 but with inputs and outputs on opposite sides.

Features

■ICC and IOZ reduced by 50%

■Inputs and outputs on opposite sides of package allowing easy interface with microprocessors

■Useful as input or output port for microprocessors

■Functionally identical to 74AC373 and 74ACT373

■3-STATE outputs for bus interfacing

■Outputs source/sink 24 mA

■74ACT573 has TTL-compatible inputs

Ordering Code:

Order Number	Package Number	Package Description
74AC573SC	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body
74AC573SJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC573MTC	MTC20	20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC573PC	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT573SC	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body
74ACT573SJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT573MTC	MTC20	20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT573PC	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

	Pin Names		Description
	D0–D7		Data Inputs
	LE		Latch Enable Input
			3-STATE Output Enable Input
	OE
	O0–O7		3-STATE Latch Outputs

FACTä is a trademark of Fairchild Semiconductor Corporation.

Outputs STATE-3 with Latch Octal 74ACT573 • 74AC573

© 1999 Fairchild Semiconductor Corporation

DS009973

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74AC573 • 74ACT573

Functional Description

The 74AC573 and 74ACT573 contain eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW the latches store the information that was

present on the D-type inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is

LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.

Truth Table

		Inputs		Outputs
OE		LE	D	On
	L	H	H	H
	L	H	L	L
	L	L	X	O0
	H	X	X	Z

H = HIGH Voltage

L = LOW Voltage

Z = High Impedance

X = Immaterial

O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings(Note 1)

Supply Voltage (VCC)	−0.5V to +7.0V
DC Input Diode Current (IIK)
VI = −0.5V	−20 mA
VI = VCC + 0.5V	+20 mA
DC Input Voltage (VI)	−0.5V to VCC + 0.5V
DC Output Diode Current (IOK)
VO = −0.5V	−20 mA
VO = VCC + 0.5V	+20 mA
DC Output Voltage (VO)	−0.5V to VCC + 0.5V
DC Output Source
or Sink Current (IO)	±50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND)	±50 mA
Storage Temperature (TSTG)	−65°C to +150°C
Junction Temperature (TJ)
(PDIP)	140°C

Recommended Operating

Conditions

Supply Voltage (VCC)
AC	2.0V to 6.0V
ACT	4.5V to 5.5V
Input Voltage (VI)	0V to VCC
Output Voltage (VO)	0V to VCC
Operating Temperature (TA)	−40°C to +85°C
Minimum Input Edge Rate ( V/	t)
AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.0V, 4.5V, 5.5V	125 mV/ns
ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V	125 mV/ns

Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTä circuits outside databook specifications.

DC Electrical Characteristics for AC

Symbol	Parameter		VCC		TA = +25°C			TA = −40°C to +85°C	Units	Conditions
			(V)		Typ		Guaranteed Limits
VIH	Minimum HIGH Level		3.0		1.5	2.1		2.1		VOUT = 0.1V
	Input Voltage		4.5		2.25	3.15		3.15	V	or VCC − 0.1V
			5.5		2.75	3.85		3.85
VIL	Maximum LOW Level		3.0		1.5	0.9		0.9		VOUT = 0.1V
	Input Voltage		4.5		2.25	1.35		1.35	V	or VCC − 0.1V
			5.5		2.75	1.65		1.65
VOH	Minimum HIGH Level		3.0		2.99	2.9		2.9		IOUT = −50 μA
	Output Voltage		4.5		4.49	4.4		4.4	V
			5.5		5.49	5.4		5.4
										VIN = VIL or VIH
			3.0			2.56		2.46	V	IOH = −12 mA
			4.5			3.86		3.76		IOH = −24 mA
			5.5			4.86		4.76		IOH = −24 mA (Note 2)
VOL	Maximum LOW Level		3.0		0.002	0.1		0.1
	Output Voltage		4.5		0.001	0.1		0.1	V	IOUT = 50 μA
			5.5		0.001	0.1		0.1
										VIN = VIL or VIH
			3.0			0.36		0.44	V	IOL = 12 mA
			4.5			0.36		0.44		IOL = 24 mA
			5.5			0.36		0.44		IOL = 24 mA (Note 2)
IIN (Note 3)	Maximum Input Leakage Current		5.5			±0.1		±1.0	μA	VI = VCC, GND
IOLD	Minimum Dynamic		5.5					75	mA	VOLD = 1.65V Max
IOHD	Output Current (Note 4)		5.5					−75	mA	VOHD = 3.85V Min
ICC	Maximum Quiescent		5.5			4.0		40.0	μA	VIN = VCC or GND
(Note 3)	Supply Current
IOZ	Maximum 3-STATE									VI (OE) = VIL, VIH
	Leakage Current		5.5			±0.25		±2.5	μA	VI = VCC, GND
										VO = VCC, GND

Note 2: All outputs loaded; thresholds on input associated with output under test.

Note 3: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.

Note 4: Maximum test duration 2.0 ms, one output loaded at a time.

74ACT573 • 74AC573

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