August 1999
Revised October 1999
74ACT533
Octal Transparent Latch with 3-STATE Outputs
General Description
The ACT533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.
Features
■ICC and IOZ reduced by 50%
■Eight latches in a single package
■3-STATE outputs drive bus lines or buffer memory address registers
■Outputs source/sink 24 mA
■Inverted version of the ACT373
■TTL-compatible inputs
Ordering Code:
Order Number |
Package Number |
Package Description |
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74ACT533SC |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body |
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74ACT533MTC |
MTC20 |
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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74ACT533PC |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code |
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Logic Symbols |
Connection Diagram |
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IEEE/IEC
Pin Descriptions
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Pin Names |
Description |
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D0–D7 |
Data Inputs |
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LE |
Latch Enable Input |
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Output Enable Input |
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OE |
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O |
0–O |
7 |
3-STATE Latch Outputs |
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FACTä is a trademark of Fairchild Semiconductor Corporation.
Outputs STATE-3 with Latch Transparent Octal 74ACT533
© 1999 Fairchild Semiconductor Corporation |
DS500311 |
www.fairchildsemi.com |
74ACT533
Functional Description
The ACT533 contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs at setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.
Logic Diagram
Truth Table
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Inputs |
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Outputs |
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LE |
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OE |
Dn |
On |
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X |
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H |
X |
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Z |
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H |
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L |
L |
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H |
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H |
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L |
H |
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L |
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L |
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L |
X |
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O |
0 |
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H = HIGH Voltage Level
L = LOW Voltage Level Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Supply Voltage (V |
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− 0.5V to + 7.0V |
CC |
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DC Input Diode Current (IIK) |
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VI = − 0.5V |
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− 20 mA |
VI = VCC + 0.5V |
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+ 20 mA |
DC Input Voltage (VI) |
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−0.5V to VCC + 0.5V |
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DC Output Diode Current (IOK) |
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VO = − 0.5V |
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− 20 mA |
VO = VCC + 0.5V |
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+ 20 mA |
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DC Output Voltage (VO) |
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− 0.5V to VCC + 0.5V |
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DC Output Source |
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or Sink Current (IO) |
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± 50 mA |
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DC VCC or Ground Current |
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per Output Pin (I |
CC |
or I |
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± 50 mA |
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GND |
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Storage Temperature (TSTG) |
− 65°C to + 150°C |
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DC Latchup Source |
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or Sink Current |
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± 300 mA |
Junction Temperature (TJ) |
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PDIP |
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140°C |
Recommended Operating
Conditions
Supply Voltage (V |
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4.5V to 5.5V |
CC |
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Input Voltage (VI) |
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0V to VCC |
Output Voltage (VO) |
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0V to VCC |
Operating Temperature (TA) |
−40°C to +85°C |
Minimum Input Edge Rate V/ |
t |
VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
125 mV/ns |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTä circuits outside databook specifications.
DC Electrical Characteristics
Symbol |
Parameter |
VCC |
TA = +25°C |
TA = −40°C to +85°C |
Units |
Conditions |
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(V) |
Typ |
Guaranteed Limits |
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VIH |
Minimum HIGH Level |
4.5 |
1.5 |
2.0 |
2.0 |
V |
VOUT = 0.1V |
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Input Voltage |
5.5 |
1.5 |
2.0 |
2.0 |
or VCC − 0.1V |
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VIL |
Maximum LOW Level |
4.5 |
1.5 |
0.8 |
0.8 |
V |
VOUT = 0.1V |
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Input Voltage |
5.5 |
1.5 |
0.8 |
0.8 |
or VCC − 0.1V |
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VOH |
Minimum HIGH Level |
4.5 |
4.49 |
4.4 |
4.4 |
V |
IOUT = −50 μA |
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Output Voltage |
5.5 |
5.49 |
5.4 |
5.4 |
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VIN = VIL or VIH |
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4.5 |
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3.86 |
3.76 |
V |
IOH = −24 mA |
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5.5 |
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4.86 |
4.76 |
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IOH = −24 mA (Note 2) |
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VOL |
Maximum LOW Level |
4.5 |
0.001 |
0.1 |
0.1 |
V |
IOUT = 50 μA |
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Output Voltage |
5.5 |
0.001 |
0.1 |
0.1 |
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VIN = VIL or VIH |
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4.5 |
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0.36 |
0.44 |
V |
IOL = 24 mA |
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5.5 |
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0.36 |
0.44 |
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IOL = 24 mA (Note 2) |
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IIN |
Maximum Input |
5.5 |
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±0.1 |
±1.0 |
μA |
VI = VCC, GND |
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Leakage Current |
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IOZ |
Maximum 3-STATE |
5.5 |
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±0.25 |
±2.5 |
μA |
VI = VIL, VIH |
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Leakage Current |
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VO = VCC, GND |
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ICCT |
Maximum |
5.5 |
0.6 |
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1.5 |
mA |
VI = VCC − 2.1V |
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ICC/Input |
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IOLD |
Minimum Dynamic |
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5.5 |
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75 |
mA |
VOLD = 1.65V Max |
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IOHD |
Output Current (Note 3) |
5.5 |
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−75 |
mA |
VOHD = 3.85V Min |
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ICC |
Maximum Quiescent |
5.5 |
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4.0 |
40.0 |
μA |
VIN = VCC |
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Supply Current |
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or GND |
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Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
74ACT533
3 |
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