Fairchild Semiconductor 74AC251SJX, 74AC251SJ, 74AC251SCX, 74AC251SC, 74AC251PC Datasheet
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November 1988
Revised November 1999
74AC251 • 74ACT251
8-Input Multiplexer with 3-STATE Output
General Description
The AC/ACT251 is a high-speed 8-input digital multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. It can be used as universal function generator to generate any logic function of four variables. Both true and complementary outputs are provided.
Features
■ICC reduced by 50%
■Multifunctional capability
■On-chip select logic decoding
■Inverting and noninverting 3-STATE outputs
■Outputs source/sink 24 mA
■ACT251 has TTL-compatible inputs
Ordering Code:
Order Number |
Package Number |
Package Description |
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74AC251SC |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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74AC251SJ |
M16D |
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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74AC251MTC |
MTC16 |
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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74AC251PC |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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74ACT251SC |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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74ACT251MTC |
MTC16 |
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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74ACT251PC |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols |
Connection Diagram |
IEEE/IEC
Pin Descriptions
Pin Names |
Description |
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S0–S2 |
Select Inputs |
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3-STATE Output Enable Input |
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OE |
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I0–I7 |
Multiplexer Inputs |
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Z |
3-STATE Multiplexer Output |
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Complementary 3-STATE Multiplexer Output |
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Z |
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FACT is a trademark of Fairchild Semiconductor Corporation.
Output STATE-3 with Multiplexer Input-8 74ACT251 • 74AC251
© 1999 Fairchild Semiconductor Corporation |
DS009945 |
www.fairchildsemi.com |
74AC251 • 74ACT251
Functional Description
This device is a logical implementation of a single-pole, 8- position switch with the switch position controlled by the state of three Select inputs, S0, S1, S2. Both true and com- plementary outputs are provided. The Output Enable input (OE) is active LOW. When it is activated, the logic function provided at the output is:
Z = |
OE |
• |
(I0 • |
S |
0 • |
S |
1 • |
S |
2 + I1• S0 • |
S |
1 • |
S |
2 + |
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I2 • |
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0 • S1 • |
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2 + |
I3 • S0 • S1 • |
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2 + |
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S |
S |
S |
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I4 • |
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0 • |
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1 • S2 + I5 • S0 • |
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1 • S2 + |
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S |
S |
S |
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I6 • |
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0 • S1 • S2 + |
I7 • S0 • S1 • S2) |
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S |
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When the Output Enable is HIGH, both outputs are in the high impedance (High Z) state. This feature allows multiplexer expansion by tying the outputs of up to 128 devices together. When the outputs of the 3-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. The Output Enable signals should be designed to ensure there is no overlap in the active-LOW portion of the enable voltages.
Logic Diagram
Truth Table
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Inputs |
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Outputs |
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OE |
S2 |
S1 |
S0 |
Z |
Z |
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H |
X |
X |
X |
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Z |
Z |
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L |
L |
L |
L |
I0 |
I0 |
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L |
L |
L |
H |
I1 |
I1 |
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L |
L |
H |
L |
I2 |
I2 |
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L |
L |
H |
H |
I3 |
I3 |
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L |
H |
L |
L |
I4 |
I4 |
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L |
H |
L |
H |
I5 |
I5 |
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L |
H |
H |
L |
I6 |
I6 |
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L |
H |
H |
H |
I7 |
I7 |
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H = |
HIGH Voltage Level |
L = |
LOW Voltage Level |
X = |
Immaterial |
Z = |
High Impedance |
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
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− 0.5V to + 7.0V |
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DC Input Diode Current (IIK) |
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VI = |
− 0.5V |
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− 20 mA |
VI = |
VCC + 0.5V |
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+ 20 mA |
DC Input Voltage (VI) |
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− 0.5V to VCC + 0.5V |
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DC Output Diode Current (IOK) |
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VO = |
− 0.5V |
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− 20 mA |
VO = |
VCC + 0.5V |
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+ 20 mA |
DC Output Voltage (VO) |
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− 0.5V to VCC + 0.5V |
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DC Output Source |
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or Sink Current (IO) |
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± 50 mA |
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DC VCC or Ground Current |
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per Output Pin (I |
or I |
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± 50 mA |
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CC |
GND |
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Storage Temperature (TSTG) |
− 65° C to + 150° C |
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Junction Temperature (TJ) |
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PDIP |
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140° C |
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Recommended Operating
Conditions
Supply Voltage (VCC) |
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AC |
2.0V to 6.0V |
ACT |
4.5V to 5.5V |
Input Voltage (V ) |
0V to V |
I |
CC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
− 40° C to + 85° C |
Minimum Input Edge Rate (∆ V/∆ t) |
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AC Devices |
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VIN from 30% to 70% of VCC |
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VCC @ 3.3V, 4.5V, 5.5V |
125 mV/ns |
Minimum Input Edge Rate (∆ V/∆ t) |
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ACT Devices |
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VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
125 mV/ns |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
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V |
TA = + 25° C |
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TA = − 40° C to + 85° C |
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Symbol |
Parameter |
CC |
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Units |
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Conditions |
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(V) |
Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH Level |
3.0 |
1.5 |
2.1 |
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2.1 |
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VOUT = |
0.1V |
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Input Voltage |
4.5 |
2.25 |
3.15 |
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3.15 |
V |
or VCC − |
0.1V |
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5.5 |
2.75 |
3.85 |
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3.85 |
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VIL |
Maximum LOW Level |
3.0 |
1.5 |
0.9 |
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0.9 |
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VOUT = |
0.1V |
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Input Voltage |
4.5 |
2.25 |
1.35 |
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1.35 |
V |
or VCC − |
0.1V |
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5.5 |
2.75 |
1.65 |
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1.65 |
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VOH |
Minimum HIGH Level |
3.0 |
2.99 |
2.9 |
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2.9 |
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Output Voltage |
4.5 |
4.49 |
4.4 |
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4.4 |
V |
IOUT = |
− |
50 µ A |
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5.5 |
5.49 |
5.4 |
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5.4 |
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VIN = |
VIL or VIH |
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3.0 |
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2.56 |
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2.46 |
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IOH = − 12 mA |
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4.5 |
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3.86 |
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3.76 |
V |
IOH = − 24 mA |
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5.5 |
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4.86 |
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4.76 |
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IOH = − 24 mA (Note 2) |
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VOL |
Maximum LOW Level |
3.0 |
0.002 |
0.1 |
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0.1 |
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Output Voltage |
4.5 |
0.001 |
0.1 |
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0.1 |
V |
IOUT = |
50 µ A |
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5.5 |
0.001 |
0.1 |
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0.1 |
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VIN = |
VIL or VIH |
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3.0 |
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0.36 |
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0.44 |
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IOL = 12 mA |
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4.5 |
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0.36 |
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0.44 |
V |
IOL = 24 mA |
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5.5 |
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0.36 |
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0.44 |
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IOL = 24 mA (Note 2) |
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IIN (Note 4) |
Maximum Input Leakage Current |
5.5 |
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± 0.1 |
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± |
1.0 |
µ A |
VI = |
VCC, GND |
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IOZ |
Maximum 3-STATE |
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VI (OE) = VIL, VIH |
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Current |
5.5 |
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± 0.25 |
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± |
2.5 |
µ A |
VI = |
VCC, VGND |
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VO = |
VCC, GND |
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IOLD |
Minimum Dynamic |
5.5 |
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75 |
mA |
VOLD = |
1.65V Max |
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IOHD |
Output Current (Note 3) |
5.5 |
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− 75 |
mA |
VOHD = |
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3.85V Min |
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ICC (Note 4) |
Maximum Quiescent Supply Curent |
5.5 |
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4.0 |
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40.0 |
µ A |
VIN = |
VCC or GND |
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Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
74ACT251 • 74AC251
3 |
www.fairchildsemi.com |
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