Analog Devices AD5301, AD5321, AD5311 Datasheet

a		+2.5 V to +5.5 V, 120 mA, 2-Wire Interface,
		Voltage Output 8-/10-/12-Bit DACs
		AD5301/AD5311/AD5321*

FEATURES

AD5301: Buffered Voltage Output 8-Bit DAC AD5311: Buffered Voltage Output 10-Bit DAC AD5321: Buffered Voltage Output 12-Bit DAC 6-Lead SOT-23 and 8-Lead mSOIC Packages Micropower Operation: 120 mA @ 3 V

2-Wire (I2C® Compatible) Serial Interface Data Readback Capability

+2.5 V to +5.5 V Power Supply

Guaranteed Monotonic By Design Over All Codes Power-Down to 50 nA @ 3 V

Reference Derived from Power Supply Power-On-Reset to Zero Volts

On-Chip Rail-to-Rail Output Buffer Amplifier Three Power-Down Functions

APPLICATIONS

Portable Battery Powered Instruments

Digital Gain and Offset Adjustment

Programmable Voltage and Current Sources

Programmable Attenuators

GENERAL DESCRIPTION

The AD5301/AD5311/AD5321 are single 8-, 10and 12-bit buffered voltage-output DACs that operate from a single +2.5 V to +5.5 V supply consuming 120 A at 3 V. The on-chip output amplifier allows rail-to-rail output swing with a slew rate of 0.7 V/ s. It uses a 2-wire (I2C compatible) serial interface that operates at clock rates up to 400 kHz. Multiple devices can share the same bus.

The reference for the DAC is derived from the power supply inputs and thus gives the widest dynamic output range. These parts incorporate a power-on-reset circuit, which ensures that the DAC output powers-up to zero volts and remains there until a valid write takes place. The parts contain a power-down feature which reduces the current consumption of the device to 50 nA at 3 V and provides software-selectable output loads while in power-down mode.

The low power consumption in normal operation make these DACs ideally suited to portable battery-operated equipment. The power consumption is 0.75 mW at 5 V, 0.36 mW at 3 V reducing to 1 W in all power-down modes.

FUNCTIONAL BLOCK DIAGRAM

VDD

			AD5301/AD5311/AD5321
SCL			REF
SDA	INTERFACE	DAC	8-/10-/12-BIT	BUFFER	VOUT
	LOGIC	REGISTER
			DAC
A0
A1*				POWER-DOWN
				LOGIC
				RESISTOR
	POWER-ON			NETWORK
	RESET
	GND			PD*

*AVAILABLE ON 8-LEAD VERSION ONLY

I2C is a registered trademark of Philips Corporation. *Protected by U.S. Patent No. 5684481, other patent pending.

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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Tel: [phone]	World Wide Web Site: http://www.analog.com
Fax: [phone]	© Analog Devices, Inc., 1999

AD5301/AD5311/AD5321–SPECIFICATIONS (VDD = +2.5 V to +5.5 V; RL = 2 kV to GND;

CL = 200 pF to GND; All specifications TMIN to TMAX unless otherwise noted.)

	B Version2
Parameter1	Min	Typ	Max	Units	Conditions/Comments
DC PERFORMANCE3, 4
AD5301
Resolution		8		Bits
Relative Accuracy		±0.15	±1	LSB
Differential Nonlinearity		±0.02	±0.25	LSB	Guaranteed Monotonic by Design Over All Codes
AD5311
Resolution		10		Bits
Relative Accuracy		±0.5	±4	LSB
Differential Nonlinearity		±0.05	±0.5	LSB	Guaranteed Monotonic by Design Over All Codes
AD5321
Resolution		12		Bits
Relative Accuracy		±2	±16	LSB
Differential Nonlinearity		±0.3	±0.8	LSB	Guaranteed Monotonic by Design Over All Codes
Zero Code Error		+5	+20	mV	All Zeros Loaded to DAC, See Figure 9
Full-Scale Error		±0.15	±1.25	% of FSR	All Ones Loaded to DAC, See Figure 9
Gain Error		±0.15	±1	% of FSR
Zero Code Error Drift5		–20		µV/°C
Gain Error Drift5		–5		ppm of FSR/°C
OUTPUT CHARACTERISTICS5
Minimum Output Voltage		0.001		V min	This is a measure of the minimum and maximum drive
Maximum Output Voltage		VDD – 0.001		V max	capability of the output amplifier.
DC Output Impedance		1		Ω
Short Circuit Current		50		mA	VDD = +5 V
		20		mA	VDD = +3 V
Power-Up Time		2.5		µs	Coming Out of Power-Down Mode. VDD = +5	V
		6		µs	Coming Out of Power-Down Mode. VDD = +3	V
LOGIC INPUTS (A0, A1, PD)5			±1	µA
Input Current					VDD = +5 V ± 10%
VIL, Input Low Voltage			0.8	V
			0.6	V	VDD = +3 V ± 10%
			0.5	V	VDD = +2.5 V
VIH, Input High Voltage	2.4			V	VDD = +5 V ± 10%
	2.1			V	VDD = +3 V ± 10%
	2.0			V	VDD = +2.5 V
Pin Capacitance		3		pF
LOGIC INPUTS (SCL, SDA)5
VIH, Input High Voltage	0.7 VDD		VDD + 0.3	V
VIL, Input Low Voltage	–0.3		0.3 VDD	V
IIN, Input Leakage Current			±1	µA	VIN = 0 V to VDD
VHYST, Input Hysteresis	0.05 VDD			V
CIN, Input Capacitance		6		pF
Glitch Rejection6			50	ns	Pulsewidth of Spike Suppressed
LOGIC OUTPUT (SDA)5
VOL, Output Low Voltage			0.4	V	ISINK = 3 mA
			0.6	V	ISINK = 6 mA
Three-State Leakage Current			±1	µA
Three-State Output Capacitance		6		pF
POWER REQUIREMENTS
VDD	2.5		5.5	V	IDD Specification Is Valid for All DAC Codes
IDD (Normal Mode)				µA	DAC Active and Excluding Load Current
VDD = +4.5 V to +5.5 V		150	250		VIH = VDD and VIL = GND
VDD = +2.5 V to +3.6 V		120	220	µA	VIH = VDD and VIL = GND
IDD (Power-Down Mode)				µA
VDD = +4.5 V to +5.5 V		0.2	1		VIH = VDD and VIL = GND
VDD = +2.5 V to +3.6 V		0.05	1	µA	VIH = VDD and VIL = GND

NOTES

1See Terminology.

2Temperature ranges are as follows: B Version: –40°C to +105°C. 3DC specifications tested with the outputs unloaded.

4Linearity is tested using a reduced code range: AD5301 (Code 7 to 250); AD5311 (Code 28 to 1000); AD5321 (Code 112 to 4000). 5Guaranteed by Design and Characterization, not production tested.

6Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.

Specifications subject to change without notice.

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						AD5301/AD5311/AD5321
1	(VDD = +2.5 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; All specifications TMIN to TMAX unless
AC CHARACTERISTICS	otherwise noted.)
Parameter2			B Version3
		Min	Typ	Max	Units	Conditions/Comments
Output Voltage Settling Time					s	VDD = +5 V
AD5301			6	8		1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex)
AD5311			7	9	s	1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex)
AD5321			8	10	s	1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex)
Slew Rate			0.7		V/ s
Major-Code Change Glitch Impulse			12		nV-s	1 LSB Change Around Major Carry
Digital Feedthrough			0.3		nV-s

NOTES

1See Terminology

2Guaranteed by design and characterization, not production tested. 3Temperature ranges are as follows: B Version: –40°C to +105°C.

Specifications subject to change without notice.

TIMING CHARACTERISTICS1 (VDD = +2.5 V to +5.5 V. All specifications TMIN to TMAX unless otherwise noted.)

Parameter2	Limit at TMIN, TMAX
	(B Version)	Units	Conditions/Comments
fSCL	400	kHz max	SCL Clock Frequency
t1	2.5	s min	SCL Cycle Time
t2	0.6	s min	tHIGH, SCL High Time
t3	1.3	s min	tLOW, SCL Low Time
t4	0.6	s min	tHD,STA, Start/Repeated Start Condition Hold Time
t5	100	ns min	tSU,DAT, Data Setup Time
t63	0.9	s max	tHD,DAT, Data Hold Time
	0	s min
t7	0.6	s min	tSU,STA, Setup Time for Repeated Start
t8	0.6	s min	tSU,STO, Stop Condition Setup Time
t9	1.3	s min	tBUF, Bus Free Time Between a STOP Condition and a START Condition
t10	300	ns max	tR, Rise Time of Both SCL and SDA when Receiving
	0	ns min	May be CMOS Driven
t11	250	ns max	tF, Fall Time of SDA when Receiving
	300	ns max	tF, Fall Time of Both SCL and SDA when Transmitting
	20 + 0.1Cb4	ns min
Cb	400	pF max	Capacitive Load for Each Bus Line

NOTES

1See Figure 1.

2Guaranteed by design and characterization, not production tested.

3A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V IH MIN of the SCL signal) in order to bridge the undefined region of SCL’s falling edge.

4Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.

Specifications subject to change without notice.

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–3–

AD5301/AD5311/AD5321

SDA

t11

t4

t9

t3

t10

SCL

t2

t4

t6

t5

t7

t8

t1

START

REPEATED

STOP

CONDITION

START

CONDITION

CONDITION

Figure 1. 2-Wire Serial Interface Timing Diagram

ABSOLUTE MAXIMUM RATINGS1, 2

(TA = +25°C unless otherwise noted)

VDD to GND . . . . . . . . . . . . . . . . . . . . . .	. . . . . –0.3 V to +7 V
SCL, SDA to GND . . . . . . . . . . . . . . . .	–0.3 V to VDD + 0.3 V
PD, A1, A0 to GND . . . . . . . . . . . . . . .	–0.3 V to VDD + 0.3 V
VOUT to GND . . . . . . . . . . . . . . . . . . . .	–0.3 V to VDD + 0.3 V
Operating Temperature Range	–40°C to +105°C
Industrial (B Version) . . . . . . . . . . . . .
Storage Temperature Range . . . . . . . . . .	. . . –65°C to +150°C
Junction Temperature (TJ max) . . . . . . . .	. . . . . . . . . . .+150°C
SOT-23 Package	(TJ max – TA)/θJA
Power Dissipation . . . . . . . . . . . . . . . .
θJA Thermal Impedance . . . . . . . . . . . .	. . . . . . . . 229.6°C/W

µSOIC Package

Power Dissipation . . . . . . . . . . . . . . . . . . . (TJ max – TA)/θJA

θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

NOTES

1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

	Temperature	Package	Package	Branding
Model	Range	Description	Option	Information
AD5301BRT	–40°C to +105°C	SOT-23	RT-6	D8B
AD5301BRM	–40°C to +105°C	µSOIC	RM-8	D8B
AD5311BRT	–40°C to +105°C	SOT-23	RT-6	D9B
AD5311BRM	–40°C to +105°C	µSOIC	RM-8	D9B
AD5321BRT	–40°C to +105°C	SOT-23	RT-6	DAB
AD5321BRM	–40°C to +105°C	µSOIC	RM-8	DAB

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5301/AD5311/AD5321 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

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AD5301/AD5311/AD5321

PIN FUNCTION DESCRIPTION

mSOIC

SOT-23

Pin No.

Pin No.

Mnemonic

Function

1

6

VDD

Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and the supply

should be decoupled with a 10 F in parallel with a 0.1 F capacitor to GND.

2

5

A0

Address Input. Sets the Least Significant Bit of the 7-bit slave address.

3

N/A

A1

Address Input. Sets the 2nd Least Significant Bit of the 7-bit slave address.

4

4

VOUT

Buffered analog output voltage from the DAC. The output amplifier has rail-to-rail operation.

5

N/A

PD

Active low control input that acts as a hardware power-down option. This pin overrides any

software power-down option. The DAC output goes three-state and the current consumption

of the part drops to 50 nA @ 3 V (200 nA @ 5 V).

6

3

SCL

Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 16-bit

input shift register. Clock rates of up to 400 kbit/s can be accommodated in the I2C compat-

ible interface. SCL may be CMOS/TTL driven.

7

2

SDA

Serial Data Line. This is used in conjunction with the SCL line to clock data into the 16-bit

input shift register during the write cycle and used to read back one or two bytes of data

(one byte for the AD5301, two bytes for the AD5311/AD5321) during the read cycle. It is

a bidirectional open-drain data line that should be pulled to the supply with an external

pull-up resistor. If not used in readback mode, SDA may be CMOS/TTL driven.

8

1

GND

Ground reference point for all circuitry on the part.

PIN CONFIGURATIONS

6-Lead SOT-23

8-Lead mSOIC

(RT-6)

(RM-8)

AD5301/AD5311/AD5321

AD5301/AD5311/AD5321

GND

VDD

VDD

GND

1

6

1

8

TOP VIEW

SDA

SDA

2

5

A0

A0

2

TOP VIEW

7

(Not to Scale)

SCL

3

4

VOUT

A1

3

(Not to Scale)

6

SCL

VOUT

PD

4

5

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