Analog Devices AD532SH, AD532SD, AD532SCHIPS, AD532KH, AD532KD Datasheet
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a |
Internally Trimmed |
Integrated Circuit Multiplier |
FEATURES
Pretrimmed to 1.0% (AD532K)
No External Components Required
Guaranteed 1.0% max 4-Quadrant Error (AD532K)
Diff Inputs for (X1 – X2) (Y1 – Y2)/10 V Transfer Function Monolithic Construction, Low Cost
APPLICATIONS
Multiplication, Division, Squaring, Square Rooting
Algebraic Computation
Power Measurements
Instrumentation Applications
Available in Chip Form
PRODUCT DESCRIPTION
The AD532 is the first pretrimmed single chip monolithic multiplier/divider. It guarantees a maximum multiplying error of
± 1.0% and a ± 10 V output voltage without the need for any external trimming resistors or output op amp. Because the AD532 is internally trimmed, its simplicity of use provides design engineers with an attractive alternative to modular multipliers, and its monolithic construction provides significant advantages in size, reliability and economy. Further, the AD532 can be used as a direct replacement for other IC multipliers that require external trim networks.
FLEXIBILITY OF OPERATION
The AD532 multiplies in four quadrants with a transfer function of (X1 – X2)(Y1 – Y2)/10 V, divides in two quadrants with a 10 V Z/(X1 – X2) transfer function, and square roots in one quadrant with a transfer function of ±√ 10 V Z. In addition to these basic functions, the differential X and Y inputs provide significant operating flexibility both for algebraic computation and transducer instrumentation applications. Transfer functions, such as XY/10 V, (X2 – Y2)/10 V, ±X2/10 V, and 10 V Z/(X1 – X2), are easily attained and are extremely useful in many modulation and function generation applications, as well as in trigonometric calculations for airborne navigation and guidance applications, where the monolithic construction and small size of the AD532 offer considerable system advantages. In addition, the high CMRR (75 dB) of the differential inputs makes the AD532 especially well qualified for instrumentation applications, as it can provide an output signal that is the product of two transducergenerated input signals.
REV. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
AD532
PIN CONFIGURATIONS
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Y2 |
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Y1 |
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VOS |
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Z |
1 |
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14 |
+VS |
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OUT |
2 |
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13 |
Y1 |
+VS |
AD532 |
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GND |
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–VS |
3 |
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12 |
Y2 |
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NC |
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AD532 |
VOS |
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TOP VIEW |
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4 |
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TOP VIEW 11 |
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Z |
(Not to Scale) |
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X2 |
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NC |
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(Not to Scale) 10 |
GND |
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NC |
6 |
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9 |
X2 |
OUT |
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X1 |
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X1 |
7 |
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8 |
NC |
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–VS |
OUT |
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NC |
+V |
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NC = NO CONNECT |
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Z |
Y |
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S |
1 |
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3 |
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1 |
20 |
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–VS 4 |
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18 |
Y2 |
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NC 5 |
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AD532 |
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NC |
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NC 6 |
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VOS |
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TOP VIEW |
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NC 7 |
(Not to Scale) |
15 |
NC |
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NC 8 |
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14 |
GND |
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9 |
10 |
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12 |
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NC |
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NC |
NC |
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X |
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NC = NO CONNECT
GUARANTEED PERFORMANCE OVER TEMPERATURE
The AD532J and AD532K are specified for maximum multiplying errors of ± 2% and ± 1% of full scale, respectively at 25°C, and are rated for operation from 0°C to 70°C. The AD532S has a maximum multiplying error of ± 1% of full scale at 25°C; it is also 100% tested to guarantee a maximum error of ± 4% at the extended operating temperature limits of –55°C and +125°C. All devices are available in either the hermetically-sealed TO-100 metal can, TO-116 ceramic DIP or LCC packages. J, K, and S grade chips are also available.
ADVANTAGES OF ON-THE-CHIP TRIMMING OF THE MONOLITHIC AD532
1.True ratiometric trim for improved power supply rejection.
2.Reduced power requirements since no networks across supplies are required.
3.More reliable since standard monolithic assembly techniques can be used rather than more complex hybrid approaches.
4.High impedance X and Y inputs with negligible circuit loading.
5.Differential X and Y inputs for noise rejection and additional computational flexibility.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 |
World Wide Web Site: http://www.analog.com |
Fax: 781/326-8703 |
© Analog Devices, Inc., 2001 |
AD532–SPECIFICATIONS (@ 25 C, VS = 15 V, R ≥ 2 k VOS grounded, unless otherwise noted.)
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AD532J |
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AD532K |
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AD532S |
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Model |
Min |
Typ |
Max |
Min |
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Typ |
Max |
Min |
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Typ |
Max |
Unit |
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MULTIPLIER PERFORMANCE |
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Transfer Function |
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(X1 – X2 )(Y1 – Y2 ) |
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(X1 – X2 )(Y1 – Y2 ) |
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(X1 – X2 )(Y1 – Y2 ) |
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10V |
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10V |
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10V |
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Total Error (–10 V ≤ X, Y ≤ +10 V) |
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±1.5 |
2.0 |
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± |
0.7 |
1.0 |
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±0.5 |
1.0 |
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TA = Min to Max |
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±2.5 |
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± |
1.5 |
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±0.01 |
4.0 |
% |
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Total Error vs. Temperature |
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±0.04 |
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± |
0.03 |
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0.04 |
%/°C |
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Supply Rejection (±15 V ± 10%) |
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±0.05 |
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± |
0.05 |
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±0.05 |
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%/% |
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Nonlinearity, X (X = 20 V p-p, Y = 10 V) |
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±0.8 |
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± |
0.5 |
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±0.5 |
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% |
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Nonlinearity, Y (Y = 20 V p-p, X = 10 V) |
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±0.3 |
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± |
0.2 |
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±0.2 |
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% |
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Feedthrough, X (Y Nulled, |
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200 |
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100 |
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100 |
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X = 20 V p-p 50 Hz) |
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50 |
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30 |
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30 |
mV |
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Feedthrough, Y (X Nulled, |
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150 |
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80 |
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80 |
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Y = 20 V p-p 50 Hz) |
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30 |
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25 |
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25 |
mV |
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Feedthrough vs. Temperature |
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2.0 |
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1.0 |
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1.0 |
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mV p-p/°C |
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Feedthrough vs. Power Supply |
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±0.25 |
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± |
0.25 |
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±0.25 |
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mV/% |
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DYNAMICS |
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Small Signal BW (VOUT = 0.1 rms) |
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1 |
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1 |
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1 |
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MHz |
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1% Amplitude Error |
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75 |
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75 |
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75 |
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kHz |
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Slew Rate (VOUT 20 p-p) |
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45 |
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45 |
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45 |
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V/µs |
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Settling Time (to 2%, ∆VOUT = 20 V) |
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1 |
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1 |
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1 |
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µs |
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NOISE |
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Wideband Noise f = 5 Hz to 10 kHz |
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0.6 |
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0.6 |
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0.6 |
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mV (rms) |
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f = 5 Hz to 5 MHz |
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3.0 |
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3.0 |
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3.0 |
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mV (rms) |
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OUTPUT |
±10 |
±13 |
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±10 |
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± |
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±10 |
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±13 |
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Output Voltage Swing |
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13 |
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V |
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Output Impedance (f ≤ 1 kHz) |
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1 |
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1 |
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1 |
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Ω |
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Output Offset Voltage |
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±40 |
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30 |
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30 |
mV |
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Output Offset Voltage vs. Temperature |
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0.7 |
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0.7 |
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2.0 |
mV/°C |
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Output Offset Voltage vs. Supply |
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±2.5 |
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± |
2.5 |
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±2.5 |
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mV/% |
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INPUT AMPLIFIERS (X, Y, and Z) |
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Signal Voltage Range (Diff. or CM |
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±10 |
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± |
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±10 |
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Operating Diff) |
40 |
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50 |
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10 |
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50 |
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V |
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CMRR |
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dB |
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Input Bias Current |
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4 |
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4 |
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µA |
X, Y Inputs |
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3 |
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1.5 |
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1.5 |
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X, Y Inputs TMIN to TMAX |
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10 |
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8 |
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8 |
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µA |
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Z Input |
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±10 |
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± |
5 |
15 |
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±5 |
15 |
µA |
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Z Input TMIN to TMAX |
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±30 |
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± |
25 |
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±25 |
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µA |
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Offset Current |
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±0.3 |
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± |
0.1 |
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±0.1 |
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µA |
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Differential Resistance |
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10 |
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10 |
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10 |
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MΩ |
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DIVIDER PERFORMANCE |
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Transfer Function (Xl > X2) |
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10 V Z/(X1 – X2) |
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10 V Z/(X1 – X2) |
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10 V Z/(X1 – X2) |
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Total Error |
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(VX = –10 V, –10 V ≤ VZ ≤ +10 V) |
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±2 |
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± |
1 |
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±1 |
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% |
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(VX = –1 V, –10 V ≤ VZ ≤ +10 V) |
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±4 |
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± |
3 |
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±3 |
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% |
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SQUARE PERFORMANCE |
(X1 – X2 )2 |
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(X1 – X2 )2 |
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(X1 – X2 )2 |
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Transfer Function |
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10V |
±0.8 |
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10V |
± |
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10V |
±0.4 |
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Total Error |
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0.4 |
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% |
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SQUARE ROOTER PERFORMANCE |
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–√10 V Z |
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–√10 V Z |
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–√10 V Z |
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Transfer Function |
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Total Error (0 V ≤ VZ ≤ 10 V) |
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±1.5 |
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± |
1.0 |
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±1.0 |
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% |
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POWER SUPPLY SPECIFICATIONS |
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Supply Voltage |
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±15 |
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± |
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±15 |
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Rated Performance |
±10 |
18 |
±10 |
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15 |
18 |
±10 |
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±22 |
V |
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Operating |
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V |
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Supply Current |
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4 |
6 |
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4 |
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6 |
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4 |
6 |
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Quiescent |
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mA |
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PACKAGE OPTIONS |
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TO-116 (D-14) |
AD532JD |
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AD532KD |
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AD532SD |
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TO-100 (H-10A) |
AD532JH |
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AD532KH |
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AD532SH |
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LCC (E-20A) |
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AD532SE/883B |
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Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
THERMAL CHARACTERISTICS
H-10A: θJC = 25°C/W; θJA = 150°C/W E-20A: θJC = 22°C/W; θJA = 85°C/W D-14: θJC = 22°C/W; θJA = 85°C/W
–2– |
REV. C |
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AD532 |
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ORDERING GUIDE |
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CHIP DIMENSIONS AND BONDING DIAGRAM |
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Contact factory for latest dimensions. |
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Temperature |
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Package |
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Package |
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Dimensions shown in inches and (mm). |
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Model |
Ranges |
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Descriptions |
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Options |
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AD532JD |
0°C to 70°C |
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Side Brazed DIP |
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D-14 |
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AD532JD/+ |
0°C to 70°C |
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Side Brazed DIP |
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D-14 |
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0.107 |
VS |
OUTPUT |
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AD532KD |
0°C to 70°C |
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Side Brazed DIP |
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D-14 |
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(2.718) |
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AD532KD/+ |
0°C to 70°C |
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Side Brazed DIP |
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D-14 |
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AD532JH |
0°C to 70°C |
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Header |
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H-10A |
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AD532KH |
0°C to 70°C |
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Header |
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H-10A |
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Z |
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AD532JCHIPS |
0°C to 70°C |
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X1 |
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AD532SD |
–55°C to +125°C |
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Side Brazed DIP |
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D-14 |
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0.062 |
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(1.575) |
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AD532SD/883B |
–55°C to +125°C |
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Side Brazed DIP |
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VS |
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JM38510/13903BCA |
–55°C to +125°C |
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Side Brazed DIP |
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Y1 |
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AD532SE/883B |
–55°C to +125°C |
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LCC |
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AD532SH |
–55°C to +125°C |
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H-10A |
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AD532SH/883B |
–55°C to +125°C |
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X2 |
GND |
VOS |
Y2 |
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JM38510/13903BIA |
–55°C to +125°C |
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AD532SCHIPS |
–55°C to +125°C |
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FUNCTIONAL DESCRIPTION |
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The functional block diagram for the AD532 is shown in Figure |
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1, and the complete schematic in Figure 2. In the multiplying |
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and squaring modes, Z is connected to the output to close the |
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feedback around the output op amp. (In the divide mode, it is |
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used as an input terminal.) |
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VX |
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X2 |
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The X and Y inputs are fed to high impedance differential |
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R |
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R |
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amplifiers featuring low distortion and good common-mode |
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X |
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Z |
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rejection. The amplifier voltage offsets are actively laser trimmed |
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Y1 |
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OUTPUT |
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to zero during production. The product of the two inputs is |
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VY |
Y2 |
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resolved in the multiplier cell using Gilbert’s linearized trans- |
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10R |
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VOS |
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conductance technique. The cell is laser trimmed to obtain |
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(X1 – X2) (Y1 – Y2) |
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R |
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VOUT = (X1 – X2)(Y1 – Y2)/10 volts. The built-in op amp is used |
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VOUT = |
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10V |
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to obtain low output impedance and make possible self-contained |
(WITH Z TIED TO OUTPUT) |
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operation. The residual output voltage offset can be zeroed at |
Figure 1. Functional Block Diagram |
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VOS in critical applications . . . otherwise the VOS pin should |
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be grounded. |
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X2 |
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VS |
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R2 |
R6 |
R8 |
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R16 |
R23 |
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R27 |
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C1 |
Z |
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Q1 |
Q2 |
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Q7 |
Q8 |
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Q14 Q15 |
Q16 Q17 |
Q21 |
R33 |
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R34 |
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R20 |
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Q25 |
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R22 |
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VOS |
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Y1 |
R9 |
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Q9 |
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Q10 |
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R1 |
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R30 |
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X1 |
Q4 |
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R13 |
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R21 |
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Q3 |
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Q22 |
R31 |
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R3 |
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Q26 |
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COM |
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R28 |
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Q18 |
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Q23 |
OUTPUT |
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R10 |
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R29 |
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Q5 |
Q6 |
Q11 |
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Q12 |
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Q24 |
Q27 |
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R32 |
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R11 |
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R19 |
Q20 |
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R14 |
Q19 |
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R4 |
Q28 |
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R12 |
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Q13 |
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R5 |
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R15 |
R24 |
R25 |
R26 |
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Y2 |
R18 |
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VS CAN |
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Figure 2. Schematic Diagram
REV. C |
–3– |
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