Analog Devices AD5260BRU50, AD5260BRU200-REEL7, AD5260BRU200, AD5260BRU20-REEL7, AD5260BRU20 Datasheet

a 15 V Digital Potentiometers1-/2-Channel

AD5260/AD5262

FEATURES 256 Positions

AD5260 – 1-Channel

AD5262 – 2-Channel (Independently Programmable) Potentiometer Replacement

20 k , 50 k , 200 k

Low Temperature Coefficient 35 ppm/ C

4-Wire SPI-Compatible Serial Data Input

5 V to 15 V Single-Supply; 5.5 V Dual-Supply Operation

Power ON Mid-Scale Preset

APPLICATIONS

Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Stereo Channel Audio Level Control Programmable Voltage to Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching

Low Resolution DAC Replacement

GENERAL DESCRIPTION

The AD5260/AD5262 provide a singleor dual-channel, 256position, digitally controlled variable resistor (VR) device.* These devices perform the same electronic adjustment function as a potentiometer or variable resistor. Each channel of the AD5260/ AD5262 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the SPI-compatible serial-input register. The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. The variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper or the B terminal and the wiper. The fixed A to B terminal resistance of 20 kΩ, 50 kΩ, or 200 kΩ has a nominal temperature coefficient of 35 ppm/∞C. Unlike the majority of the digital potentiometers in the market, these devices can operate up to 15 V or ±5 V provided proper supply voltages are furnished.

Each VR has its own VR latch, which holds its programmed resistance value. These VR latches are updated from an internal serial-to-parallel shift register, which is loaded from a standard 3-wire serial-input digital interface. The AD5260 contains an 8-bit serial register while the AD5262 contains a 9-bit serial register. Each bit is clocked into the register on the positive edge of the CLK. The AD5262 address bit determines the corresponding VR latch to be loaded with the last 8 bits of the data word during the positive edging of CS strobe. A serial data output pin at the opposite end of the serial register enables simple daisy chaining in multiple VR applications without additional external decoding logic. An optional reset pin (PR) forces the wiper to the mid-scale position by loading 80H into the VR latch.

FUNCTIONAL BLOCK DIAGRAMS

		A	W B
	SHDN		AD5260
	VDD		RDAC
	VSS	REGISTER
	VL		POWER-ON
				PR
	CS	LOGIC	RESET

8

CLK

SERIAL INPUT REGISTER SDO

SDI

GND

			A1	W1	B1	A2	W2	B2
SHDN
	VDD
	VSS		RDAC1 REGISTER			RDAC2 REGISTER
		VL
		CS					POWER-ON		PR
			LOGIC				RESET
						8
	CLK			SERIAL INPUT REGISTER					SDO
		SDI
	GND				AD5262
		100
			RWA					RWB
	AB
	R
PERCENT OF NOMINAL	END-TO-END RESISTANCE – %	75
		50
		25
		0 0		64	128		192		256

CODE – Decimal

Figure 1. RWA and RWB vs. Code

*The terms digital potentiometers, VR, and RDAC are used interchangeably.

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

The AD5260/AD5262 are available in thin surface-mount TSSOP-14 and TSSOP-16 packages. All parts are guaranteed to operate over the extended industrial temperature range of Ð40∞C to +85∞C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: [phone]	www.analog.com
Fax: [phone]	© Analog Devices, Inc., 2002

		(VDD = +15 V, VSS = 0 V or, VDD = +5 V, VSS = –5 V, VL = +5 V, VA = +5 V,
AD5260/AD5262–SPECIFICATIONS VB = 0 V, – 40 C < TA < +85 C unless otherwise noted.)
ELECTRICAL CHARACTERISTICS 20 kΩ, 50 kΩ, 200 kΩ VERSIONS
Parameter	Symbol	Conditions	Min	Typ1	Max	Unit
DC CHARACTERISTICS RHEOSTAT	MODE Specifications apply to all VRs			±1/4
Resistor Differential NL2	R-DNL	RWB, VA = NC	Ð1		+1	LSB
Resistor Nonlinearity2	R-INL	RWB, VA = NC	Ð1	±1/2	+1	LSB
Nominal Resistor Tolerance3	RAB	TA = 25∞C	Ð30		30	%
Resistance Temperature Coefficient	RAB/ T	Wiper = No Connect		35		ppm/∞C
Wiper Resistance	RW	IW = 1 V/RAB		60	150	Ω
Channel Resistance Matching (AD5262 only)	RWB/RWB	Ch 1 and 2 RWB, DX = 80H		0.1		%
Resistance Drift	RAB			0.05		%
DC CHARACTERISTICS POTENTIOMETER DIVIDER		MODE Specifications apply to all VRs
Resolution	N		8	±1/4		Bits
Differential Nonlinearity4	DNL		Ð1		+1	LSB
Integral Nonlinearity4	INL		Ð1	±1/2	+1	LSB
Voltage Divider Temperature Coefficient	VW/ T	Code = 80H		5		ppm/∞C
Full-Scale Error	VWFSE	Code = FFH	Ð2	Ð1	+0	LSB
Zero-Scale Error	VWZSE	Code = 00H	0	1	2	LSB
RESISTOR TERMINALS
Voltage Range5	VA, B, W		VSS		VDD	V
Capacitance6 Ax, Bx	CA,B	f = 5 MHz,		25		pF
Capacitance6 Wx		measured to GND, Code = 80H
	CW	f = 1 MHz,		55		pF
		measured to GND, Code = 80H
Common-Mode Leakage Current	ICM	VA =VB = VDD /2		1		nA
Shut Down Current7	ISHDN				5	μA
DIGITAL INPUTS and OUTPUTS
Input Logic High	VIH		2.4			V
Input Logic Low	VIL				0.8	V
Input Logic High	VIH	VL = 3 V, VSS = 0 V	2.1			V
Input Logic Low	VIL	VL = 3 V, VSS = 0 V			0.6	V
Output Logic High (SDO)	VOH	RPULL-UP = 2 kΩ to 5 V	4.9			V
Output Logic Low (SDO)	VOL	IOL = 1.6 mA, VLOGIC = 5 V			0.4	V
Input Current8	IIL	VIN = 0 V or 5 V			±1	μA
Input Capacitance6	CIL			5		pF
POWER SUPPLIES
Logic Supply	VL		2.7		5.5	V
Power Single-Supply Range	VDD RANGE	VSS = 0 V	4.5		16.5	V
Power Dual-Supply Range	VDD/SS RANGE		±4.5		±5.5	V
Logic Supply Current	IL	VL = 5 V			60	μA
Positive Supply Current	IDD	VIH = 5 V or VIL = 0 V			1	μA
Negative Supply Current	ISS	VSS = Ð5 V			1	μA
Power Dissipation9	PDISS	VIH = 5 V or VIL = 0 V,			0.3	mW
		VDD = +5 V, VSS = Ð5 V
Power Supply Sensitivity	PSS	VDD = +5 V, ±10%		0.003	0.01	%/%
DYNAMIC CHARACTERISTICS6, 10		RAB = 20 kΩ/50 kΩ/200 kΩ
Bandwidth Ð3 dB	BW			310/130/30		kHz
Total Harmonic Distortion	THDW	VA = 1 VRMS, VB = 0 V,		0.014		%
VW Settling Time		f = 1 kHz, RAB = 20 kΩ				μs
	tS	VA = +5 V, VB = Ð5 V,		5
Crosstalk11		±1 LSB error band, RAB = 20 kΩ
	CT	VA = VDD, VB = 0 V,
		Measure VW with Adjacent
		RDAC Making Full-Scale		1		nVÐs
		Code Change (AD5262 only)
Analog Crosstalk	CTA	VA1 = VDD, VB1 = 0V,
		Measure VW1 with
		VW2 = 5 V p-p @ f = 10 kHz,		Ð64		dB
		RAB = 20 kΩ/200 kΩ (AD5262 only)				nV/ Hz
Resistor Noise Voltage	eN_WB	RWB = 20 kΩ		13
		f = 1 kHz

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AD5260/AD5262

Parameter		Symbol		Conditions	Min Typ	Max	Unit
INTERFACE TIMING CHARACTERISTICS		apply to		all parts6, 12
Clock Frequency		fCLK				25	MHz
Input Clock Pulsewidth		tCH, tCL		Clock level high or low	20		ns
Data Setup Time		tDS			10		ns
Data Hold Time		tDH		RL = 1 kΩ, CL < 20pF	10		ns
CLK to SDO Propagation Delay13		tPD			1	160	ns
CS Setup Time		tCSS			5		ns
CS High Pulsewidth		tCSW			20		ns
Reset Pulsewidth		tRS			50		ns
CLK Fall to CS Rise Hold Time		tCSH			0		ns
CS Rise to Clock Rise Setup		tCS1			10		ns

NOTES

The AD5260/AD5262 contains 1,968 transistors. Die Size: 89 mil. × 105 mil. 9,345 sq. mil. 1 Typicals represent average readings at 25°C and VDD = +5 V, VSS = –5 V.

2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W = VDD/R for both VDD = +5 V, VSS = –5 V.

3 VAB = VDD, Wiper (VW) = No connect.

4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = V DD and VB = 0V. DNL specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions.

5 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test.

7 Measured at the Ax terminals. All Ax terminals are open-circuit in shutdown mode.

8 Worst-case supply current consumed when input all logic-input levels set at 2.4 V, standard characteristic of CMOS logic. 9 PDISS is calculated from (IDD VDD). CMOS logic level inputs result in minimum power dissipation.

10All dynamic characteristics use VDD = +5 V, VSS = –5 V, VL = +5 V.

11Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.

12See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using VL = 5 V.

13Propagation delay depends on value of VDD, RL, and CL.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS1

(TA = 25°C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . .	. . –0.3 V, +15 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 0 V, –7 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . 15 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . .	. . . . . . VSS, VDD
AX – BX, AX – WX, BX – WX	±20 mA
Intermittent2 . . . . . . . . . . . . . . . . . . . . . . .
Continuous . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . ±5 mA
Digital Inputs and Output Voltage to GND .	. . . . . . 0 V, 7 V
Operating Temperature Range . . . . . . . . . . . .	–40°C to +85°C
Maximum Junction Temperature (TJ MAX) . . .	. . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . .	–65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . .	. 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .	. 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .	. 220°C
Thermal Resistance3 θJA	206°C/W
TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W

NOTES

1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

2Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance setting. 3Package Power Dissipation = (TJ MAX – TA)/ θJA

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AD5260/AD5262

ORDERING GUIDE

	RAB (kΩ)		Package	Package	No. of Parts	Branding
Model		Temperature	Description	Option	per Container	Information*
AD5260BRU20	20	Ð40∞C to +85∞C	TSSOP-14	RU-14	96	AD5260B20
AD5260BRU20-REEL7	20	Ð40∞C to +85∞C	TSSOP-14	RU-14	1000	AD5260B20
AD5260BRU50	50	Ð40∞C to +85∞C	TSSOP-14	RU-14	96	AD5260B50
AD5260BRU50-REEL7	50	Ð40∞C to +85∞C	TSSOP-14	RU-14	1000	AD5260B50
AD5260BRU200	200	Ð40∞C to +85∞C	TSSOP-14	RU-14	96	AD5260B200
AD5260BRU200-REEL7	200	Ð40∞C to +85∞C	TSSOP-14	RU-14	1000	AD5260B200
AD5262BRU20	20	Ð40∞C to +85∞C	TSSOP-16	RU-16	96	AD5262B20
AD5262BRU20-REEL7	20	Ð40∞C to +85∞C	TSSOP-16	RU-16	1000	AD5262B20
AD5262BRU50	50	Ð40∞C to +85∞C	TSSOP-16	RU-16	96	AD5262B50
AD5262BRU50-REEL7	50	Ð40∞C to +85∞C	TSSOP-16	RU-16	1000	AD5262B50
AD5262BRU200	200	Ð40∞C to +85∞C	TSSOP-16	RU-16	96	AD5262B200
AD5262BRU200-REEL7	200	Ð40∞C to +85∞C	TSSOP-16	RU-16	1000	AD5262B200

*Line 1 contains part number, line 2 contains differentiating detail by part type and ADI logo symbol, line 3 contains date code YWW.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5260/AD5262 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

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AD5260/AD5262

Table I. AD5260 8-Bit Serial-Data Word Format

DATA

B7	B6	B5	B4	B3	B2	B1	B0
D7	D6	D5	D4	D3	D2	D1	D0
MSB							LSB
27							20

SDI	1
	D7	D6	D5	D4	D3	D2	D1	D0
	0

1

CLK

0

1

CS RDAC REGISTER LOAD 0

1 VOUT 0

Figure 2a. AD5260 Timing Diagram

SDI	1
	A0	D7	D6	D5	D4	D3	D2	D1	D0

0

1

CLK

0

1

CS RDAC REGISTER LOAD 0

1 VOUT 0

Figure 2b. AD5262 Timing Diagram

Table II. AD5262 9-Bit Serial-Data Word Format

ADDR

DATA

B8

B7

B6

B5

B4

B3

B2

B1

B0

A0

D7

D6

D5

D4

D3

D2

D1

D0

MSB

LSB

28

27

20

SDI

1

Ax OR Dx

Dx

(DATA IN)

0

tDS

tDH

SDO

1

A x OR D x

D x

(DATA OUT)

0

tPD_MAX

tCH

CLK

1

tCS1

0

tCSH

1

tCSS

tCL

CS

tCSW

0

tS

VOUT

VDD

1 LSB

0V

1 LSB ERROR BAND

Figure 2c. Detail Timing Diagram

1

PR

tRS

0

tS

V

VDD

1 LSB

OUT

0V 1 LSB ERROR BAND

Figure 2d. Preset Timing Diagram

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AD5260/AD5262

AD5260 PIN CONFIGURATION

	A			14	SDO
		1
	W			13	NC
		2
	B			12	VL
		3
	VDD		AD5260	11	VSS
		4
	SHDN		TOP VIEW	10	GND
		5
			(Not to Scale)
	CLK			9	PR
		6
	SDI			8	CS
		7

AD5260 PIN FUNCTION DESCRIPTIONS

Pin
Number	Mnemonic	Description
1	A	A Terminal
2	W	Wiper Terminal
3	B	B Terminal
4	VDD	Positive power supply, specified
		for operation at both 5 V or 15 V.
		(Sum of |VDD| + |VSS| ≤ 15 V)
5	SHDN	Active low input. Terminal A
		open-circuit. Shutdown controls.
		Variable Resistors of RDAC.
6	CLK	Serial Clock Input, positive edge
		triggered.
7	SDI	Serial Data Input
8	CS	Chip Select Input, Active Low.
		When CS returns high, data will
		be loaded into the RDAC register.
9	PR	Active low preset to mid-scale; sets
		RDAC registers to 80H.
10	GND	Ground
11	VSS	Negative Power Supply, specified
		for operation from 0 V to Ð5 V.
12	VL	Logic Supply Voltage, needs to be
		same voltage as the digital logic
		controlling the AD5260.
13	NC	No Connect (Users should not
		connect anything other than dummy
		pad on this pin)
14	SDO	Serial Data Output, Open Drain
		transistor requires pull-up resistor.

AD5262 PIN CONFIGURATION

SDO			16	A2
	1
A1			15	W2
	2
W1			14	B2
	3
B1		AD5262	13	VL
	4
VDD		TOP VIEW	12	V
	5
		(Not to Scale)		SS
SHDN			11	GND
	6
CLK			10	PR
	7
SDI	8		9	CS

AD5262 PIN FUNCTION DESCRIPTIONS

Pin
Number	Mnemonic	Description
1	SDO	Serial Data Output, Open Drain
		transistor requires pull-up resistor.
2	A1	A Terminal RDAC #1
3	W1	Wiper RDAC #1, address A0 = 02
4	B1	B Terminal RDAC #1
5	VDD	Positive power supply, specified for
		operation at both 5 V or 15 V.
		(Sum of |VDD|+|VSS|≤ 15 V)
6	SHDN	Active low input. Terminal A
		open-circuit. Shutdown controls
		Variable Resistors #1 through #2.
7	CLK	Serial Clock Input, positive edge
		triggered.
8	SDI	Serial Data Input.
9	CS	Chip Select Input, Active Low.
		When CS returns high, data in
		the serial input register is decoded,
		based on the address Bit A0, and
		loaded into the target RDAC register.
10	PR	Active low preset to mid-scale sets
		RDAC registers to 80H.
11	GND	Ground
12	VSS	Negative Power Supply, specified
		for operation at both 0 V or Ð5 V
		(Sum of |VDD| + |VSS| <15 V).
13	VL	Logic Supply Voltage, needs to be
		same voltage as the digital logic
		controlling the AD5262.
14	B2	B Terminal RDAC #2
15	W2	Wiper RDAC #2, address A0 = 12
16	A2	A Terminal RDAC #2

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