Analog Devices AD5344BRU, AD5344, AD5336BRU, AD5336, AD5335BRU Datasheet

a 2.5 V to 5.5 V, 500 A, Parallel Interface

Quad Voltage-Output 8-/10-/12-Bit DACs

AD5334/AD5335/AD5336/AD5344*

FEATURES

AD5334: Quad 8-Bit DAC in 24-Lead TSSOP AD5335: Quad 10-Bit DAC in 24-Lead TSSOP AD5336: Quad 10-Bit DAC in 28-Lead TSSOP AD5344: Quad 12-Bit DAC in 28-Lead TSSOP

Low Power Operation: 500 A @ 3 V, 600 A @ 5 V

Power-Down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin 2.5 V to 5.5 V Power Supply

Double-Buffered Input Logic

Guaranteed Monotonic by Design Over All Codes

Output Range: 0–VREF or 0–2 VREF Power-On Reset to Zero Volts

Simultaneous Update of DAC Outputs via LDAC Pin Asynchronous CLR Facility

Low Power Parallel Data Interface

On-Chip Rail-to-Rail Output Buffer Amplifiers Temperature Range: –40 C to +105 C

APPLICATIONS

Portable Battery-Powered Instruments

Digital Gain and Offset Adjustment

Programmable Voltage and Current Sources

Programmable Attenuators

Industrial Process Control

GENERAL DESCRIPTION

The AD5334/AD5335/AD5336/AD5344 are quad 8-, 10-, and 12-bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 500 µA at 3 V, and feature a power-down mode that further reduces the current to 80 nA. These devices incorporate an on-chip output buffer that can drive the output to both supply rails.

The AD5334/AD5335/AD5336/AD5344 have a parallel interface. CS selects the device and data is loaded into the input registers on the rising edge of WR.

The GAIN pin on the AD5334 and AD5336 allows the output range to be set at 0 V to VREF or 0 V to 2 × VREF.

Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the LDAC pin.

On the AD5334, AD5335 and AD5336 an asynchronous CLR input is also provided. This resets the contents of the Input Register and the DAC Register to all zeros. These devices also incorporate a power-on-reset circuit that ensures that the DAC output powers on to 0 V and remains there until valid data is written to the device.

The AD5334/AD5335/AD5336/AD5344 are available in Thin Shrink Small Outline Packages (TSSOP).

AD5334 FUNCTIONAL BLOCK DIAGRAM

(Other Diagrams Inside)

				VREFA/B	VDD
	POWER-ON				AD5334
	RESET
GAIN
DB	INPUT	DAC	8-BIT	BUFFER		V		A
. 7	REGISTER	REGISTER					OUT
.			DAC
.
DB0
CS	INPUT	DAC
			8-BIT	BUFFER		VOUTB
	REGISTER	REGISTER
WR			DAC
	INTER-
A0	FACE
	LOGIC
A1	INPUT	DAC	8-BIT
	REGISTER	REGISTER	8-BIT	BUFFER		VOUTC
			DACDAC
	INPUT	DAC	8-BIT	BUFFER		VOUTD
	REGISTER	REGISTER	DAC
CLR				TO ALL DACS
				AND BUFFERS
LDAC					POWER-DOWN
					LOGIC
				VREFC/D	PD	GND

*Protected by U.S. Patent Number 5,969,657; other patents pending.

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: [phone]	World Wide Web Site: http://www.analog.com
Fax: [phone]	© Analog Devices, Inc., 2000

AD5334/AD5335/AD5336/AD5344–SPECIFICATIONS

(VDD = 2.5 V to 5.5 V, VREF = 2 V. RL = 2 k to GND; CL =200 pF to GND; all specifications TMIN to TMAX unless otherwise noted.)

Parameter1		B Version2
	Min	Typ	Max	Unit	Conditions/Comments
DC PERFORMANCE3, 4
AD5334
Resolution		8		Bits
Relative Accuracy		±0.15	±1	LSB
Differential Nonlinearity		±0.02	±0.25	LSB	Guaranteed Monotonic By Design Over All Codes
AD5335/AD5336
Resolution		10		Bits
Relative Accuracy		±0.5	±4	LSB
Differential Nonlinearity		±0.05	±0.5	LSB	Guaranteed Monotonic By Design Over All Codes
AD5344
Resolution		12		Bits
Relative Accuracy		±2	±16	LSB
Differential Nonlinearity		±0.2	±1	LSB	Guaranteed Monotonic By Design Over All Codes
Offset Error		±0.4	±3	% of FSR
Gain Error		±0.1	±1	% of FSR
Lower Deadband5		10	60	mV	Lower Deadband Exists Only if Offset Error Is Negative
Upper Deadband		10	60	mV	VDD = 5 V. Upper Deadband Exists Only if VREF = VDD
Offset Error Drift6		–12		ppm of FSR/°C
Gain Error Drift6		–5		ppm of FSR/°C	∆VDD = ±10%
DC Power Supply Rejection Ratio6		–60		dB
DC Crosstalk6		200		µV	RL = 2 kΩ to GND, 2 kΩ to VDD; CL = 200 pF to GND;
					Gain = 0
DAC REFERENCE INPUT6
VREF Input Range	0.25		VDD	V
VREF Input Impedance		180		kΩ	Gain = 1. Input Impedance = RDAC (AD5336/AD5344)
		90		kΩ	Gain = 2. Input Impedance = RDAC (AD5336)
		90		kΩ	Gain = 1. Input Impedance = RDAC (AD5334/AD5335)
		45		kΩ	Gain = 2. Input Impedance = RDAC (AD5334)
Reference Feedthrough		–90		dB	Frequency = 10 kHz
Channel-to-Channel Isolation		–90		dB	Frequency = 10 kHz
OUTPUT CHARACTERISTICS6
Minimum Output Voltage4, 7		0.001		V min	Rail-to-Rail Operation
Maximum Output Voltage4, 7		VDD – 0.001		V max
DC Output Impedance		0.5		Ω
Short Circuit Current		50		mA	VDD = 5 V
		20		mA	VDD = 3 V
Power-Up Time		2.5		µs	Coming Out of Power-Down Mode. VDD = 5 V
		5		µs	Coming Out of Power-Down Mode. VDD = 3 V
LOGIC INPUTS6		±1		µA
Input Current					VDD = 5 V ± 10%
VIL, Input Low Voltage			0.8	V
			0.6	V	VDD = 3 V ± 10%
			0.5	V	VDD = 2.5 V
VIH, Input High Voltage	2.4			V	VDD = 5 V ± 10%
	2.1			V	VDD = 3 V ± 10%
	2.0			V	VDD = 2.5 V
Pin Capacitance		3.5		pF
POWER REQUIREMENTS
VDD	2.5		5.5	V
IDD (Normal Mode)				µA	All DACs active and excluding load currents.
VDD = 4.5 V to 5.5 V		600	900		VIH = VDD, VIL = GND.
VDD = 2.5 V to 3.6 V		500	700	µA	IDD increases by 50 µA at VREF > VDD – 100 mV.
IDD (Power-Down Mode)				µA
VDD = 4.5 V to 5.5 V		0.2	1
VDD = 2.5 V to 3.6 V		0.08	1	µA

NOTES

1See Terminology section.

2Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.

3Linearity is tested using a reduced code range: AD5334 (Code 8 to 255); AD5335/AD5336 (Code 28 to 1023); AD5344 (Code 115 to 4095). 4DC specifications tested with outputs unloaded.

5This corresponds to x codes. x = Deadband voltage/LSB size. 6Guaranteed by design and characterization, not production tested.

7In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, VREF = VDD and “Offset plus Gain” Error must be positive.

Specifications subject to change without notice.

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						AD5334/AD5335/AD5336/AD5344
1	(VDD = 2.5 V to 5.5 V. RL = 2 k to GND; CL = 200 pF to GND. All specifications TMIN to TMAX unless other-
AC CHARACTERISTICS	wise noted.)
Parameter2			B Version3
		Min	Typ	Max	Unit		Conditions/Comments
Output Voltage Settling Time					s		VREF = 2 V. See Figure 20
AD5334			6	8			1/4 Scale to 3/4 Scale Change (40 H to C0 H)
AD5335			7	9	s		1/4 Scale to 3/4 Scale Change (100 H to 300 H)
AD5336			7	9	s		1/4 Scale to 3/4 Scale Change (100 H to 300 H)
AD5344			8	10	s		1/4 Scale to 3/4 Scale Change (400 H to C00 H)
Slew Rate			0.7		V/ s
Major Code Transition Glitch Energy			8		nV-s		1 LSB Change Around Major Carry
Digital Feedthrough			0.5		nV-s
Digital Crosstalk			3		nV-s
Analog Crosstalk			0.5		nV-s
DAC-to-DAC Crosstalk			3.5		nV-s		VREF = 2 V ± 0.1 V p-p. Unbuffered Mode
Multiplying Bandwidth			200		kHz
Total Harmonic Distortion			–70		dB		VREF = 2.5 V ± 0.1 V p-p. Frequency = 10 kHz

NOTES

1Guaranteed by design and characterization, not production tested.

2See Terminology section.

3Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.

Specifications subject to change without notice.

TIMING CHARACTERISTICS1, 2, 3 (VDD = 2.5 V to 5.5 V, All specifications TMIN to TMAX unless otherwise noted.)

Parameter	Limit at TMIN, TMAX	Unit	Condition/Comments
t1	0	ns min	CS to WR Setup Time
t2	0	ns min	CS to WR Hold Time
t3	20	ns min	WR Pulsewidth
t4	5	ns min	Data, GAIN, HBEN Setup Time
t5	4.5	ns min	Data, GAIN, HBEN Hold Time
t6	5	ns min	Synchronous Mode. WR Falling to LDAC Falling.
t7	5	ns min	Synchronous Mode. LDAC Falling to WR Rising.
t8	4.5	ns min	Synchronous Mode. WR Rising to LDAC Rising.
t9	5	ns min	Asynchronous Mode. LDAC Rising to WR Rising.
t10	4.5	ns min	Asynchronous Mode. WR Rising to LDAC Falling.
t11	20	ns min	LDAC Pulsewidth
t12	20	ns min	CLR Pulsewidth
t13	50	ns min	Time Between WR Cycles
t14	20	ns min	A0, A1 Setup Time
t15	0	ns min	A0, A1 Hold Time

NOTES

1Guaranteed by design and characterization, not production tested. 2All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3See Figure 1.

Specifications subject to change without notice.

t1

t2

CS

t3

WR

t13

t5

DATA,

t4

GAIN,

HBEN

t8

t6

LDAC1

t7

LDAC2

t9

t10

t11

CLR

t14

t15

t12

A0,

A1

NOTES:

1SYNCHRONOUS LDAC UPDATE MODE

2ASYNCHRONOUS LDAC UPDATE MODE

Figure 1. Parallel Interface Timing Diagram

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AD5334/AD5335/AD5336/AD5344

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C unless otherwise noted)

VDD to GND . . . . . . . . . . . . . . . .	. . . . . . . . .	. –0.3 V to +7 V
Digital Input Voltage to GND . . .	. . . . .–0.3 V to VDD + 0.3		V
Digital Output Voltage to GND .	. . . . . –0.3 V to VDD + 0.3		V
Reference Input Voltage to GND	. . . . –0.3 V to VDD + 0.3		V
VOUT to GND . . . . . . . . . . . . . . .	. . . . –0.3 V to VDD + 0.3		V
Operating Temperature Range		–40°C to +105°C
Industrial (B Version) . . . . . . .	. . . . . . . .
Storage Temperature Range . . . .	. . . . . . . .	–65°C to +150°C
Junction Temperature . . . . . . . . .	. . . . . . . . .	. . . . . . . . 150°C
TSSOP Package	(TJ max – TA)/θJA mW
Power Dissipation . . . . . . . . . . .
θJA Thermal Impedance (24-Lead TSSOP)		. . . . . 128°C/W
θJA Thermal Impedance (28-Lead TSSOP)		. . . . . 97.9°C/W
θJC Thermal Impedance (24-Lead TSSOP)		. . . . . . 42°C/W
θJC Thermal Impedance (28-Lead TSSOP)		. . . . . . 14°C/W

Reflow Soldering	220 +5/–0°C
Peak Temperature . . . . . . . . . . . . . . . . . . . .
Time at Peak Temperature . . . . . . . . . . . . .	10 sec to 40 sec

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model	Temperature Range	Package Description	Package Option
AD5334BRU	–40°C to +105°C	TSSOP (Thin Shrink Small Outline Package)	RU-24
AD5335BRU	–40°C to +105°C	TSSOP (Thin Shrink Small Outline Package)	RU-24
AD5336BRU	–40°C to +105°C	TSSOP (Thin Shrink Small Outline Package)	RU-28
AD5344BRU	–40°C to +105°C	TSSOP (Thin Shrink Small Outline Package)	RU-28

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5334/AD5335/AD5336/AD5344 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

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AD5334/AD5335/AD5336/AD5344

AD5334 FUNCTIONAL BLOCK DIAGRAM

AD5334 PIN CONFIGURATION

VREFA/B

VDD

VREFC/D

1

24

CLR

POWER-ON

AD5334

VREFA/B

2

23

GAIN

RESET

VOUTA

DB7

GAIN

3

22

VOUTB

4

21

DB6

DB

INPUT

DAC

8-BIT

8-BIT

BUFFER

V

A

. 7

REGISTER

REGISTER

OUT

V

C

5

20

DB

.

DAC

OUT

AD5334

5

.

DB0

VOUTD

6

TOP VIEW

19

DB4

CS

GND

7

(Not to Scale) 18

DB

3

INPUT

DAC

8-BIT

BUFFER

VOUTB

CS

8

17

DB2

REGISTER

REGISTER

WR

DAC

DB1

WR

9

16

INTER-

A0

FACE

A0 10

15

DB0

LOGIC

A1

11

14

VDD

INPUT

DAC

A1

8-BIT8-BIT

BUFFER

VOUTC

LDAC 12

13

PD

REGISTER

REGISTER

DACDAC

INPUT

DAC

8-BIT

BUFFER

VOUTD

REGISTER

REGISTER

DAC

CLR

TO ALL DACS

AND BUFFERS

LDAC

POWER-DOWN

LOGIC

VREFC/D

PD

GND

		AD5334 PIN FUNCTION DESCRIPTIONS
Pin
No.	Mnemonic	Function
1	VREFC/D	Unbuffered Reference Input for DACs C and D.
2	VREFA/B	Unbuffered Reference Input for DACs A and B.
3	VOUTA	Output of DAC A. Buffered Output with Rail-to-Rail Operation.
4	VOUTB	Output of DAC B. Buffered Output with Rail-to-Rail Operation.
5	VOUTC	Output of DAC C. Buffered Output with Rail-to-Rail Operation.
6	VOUTD	Output of DAC D. Buffered Output with Rail-to-Rail Operation.
7	GND	Ground Reference Point for All Circuitry on the Part.
8	CS	Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
9	WR	Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
10	A0	LSB Address Pin for Selecting which DAC Is to Be Written to.
11	A1	MSB Address Pin for Selecting which DAC Is to Be Written to.
12	LDAC	Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers.
		This allows all DAC outputs to be simultaneously updated.
13	PD	Power-Down Pin. This active low control pin puts all DACs into power-down mode.
14	VDD	Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
		10 F capacitor in parallel with a 0.1 F capacitor to GND.
15–22	DB0–DB7	Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
23	GAIN	Gain Control Pin. This controls whether the output range from the DAC is 0–VREF or 0–2 VREF
24	CLR	Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros.

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AD5334/AD5335/AD5336/AD5344

AD5335 FUNCTIONAL BLOCK DIAGRAM

AD5335 PIN CONFIGURATION

VREFA/B

VDD

POWER-ON

VREFC/D

1

24

CLR

RESET

AD5335

VREFA/B

2

23

HBEN

VOUTA

3

22

DB7

HIGH BYTE

REGISTER

VOUTB

4

10-BIT

21

DB6

DB

VOUTC

5

20

DB5

AD5335

. 7

.

V

D

6

19

DB

.

LOW BYTE

OUT

TOP VIEW

.

DAC

10-BIT

4

.

.

REGISTER

REGISTER

DAC

BUFFER

VOUTA

GND

7

(Not to Scale) 18

DB3

DB0

CS

8

17

DB2

CS

HIGH BYTE

WR

9

16

DB1

WR

REGISTER

A0 10

15

DB0

A1

11

14

VDD

A0

LOW BYTE

DAC

10-BIT

LDAC 12

13

PD

REGISTER

REGISTER

BUFFER

VOUTB

DAC

A1

INTER-

FACE

LOGIC

HBEN

HIGH BYTE

REGISTER

LOW BYTE

DAC

10-BIT

BUFFER

VOUTC

REGISTER

REGISTER

DAC

HIGH BYTE

REGISTER

LOW BYTE

DAC

10-BIT

BUFFER

VOUTD

REGISTER

REGISTER

DAC

CLR

RESET

TO ALL DACS

AND BUFFERS

LDAC

POWER-DOWN

LOGIC

VREFC/D

PD

GND

		AD5335 PIN FUNCTION DESCRIPTIONS
Pin
No.	Mnemonic	Function
1	VREFC/D	Unbuffered Reference Input for DACs C and D.
2	VREFA/B	Unbuffered Reference Input for DACs A and B.
3	VOUTA	Output of DAC A. Buffered output with rail-to-rail operation.
4	VOUTB	Output of DAC B. Buffered output with rail-to-rail operation.
5	VOUTC	Output of DAC C. Buffered output with rail-to-rail operation.
6	VOUTD	Output of DAC D. Buffered output with rail-to-rail operation.
7	GND	Ground Reference Point for All Circuitry on the Part.
8	CS	Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
9	WR	Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
10	A0	LSB Address Pin for Selecting which DAC Is to Be Written to.
11	A1	MSB Address Pin for Selecting which DAC Is to Be Written to.
12	LDAC	Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers.
		This allows all DAC outputs to be simultaneously updated.
13	PD	Power-Down Pin. This active low control pin puts all DACs into power-down mode.
14	VDD	Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
		10 F capacitor in parallel with a 0.1 F capacitor to GND.
15–22	DB0–DB7	Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
23	HBEN	This pin is used when writing to the device to determine if data is written to the high byte register or the
		low byte register.
24	CLR	Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros.

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