ANALOG DEVICES AD5251, AD5252 Service Manual

Dual 64-/256-Position I2C® Nonvolatile

Memory Digital Potentiometers

AD5251/AD5252

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AD5251: Dual 64-position resolution

AD5252: Dual 256-position resolution

VDD

RDAC EEMEM

RDAC1

A1

RDAC1

VSS

EEMEM

RAB

1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ

REGIS-

W1

POWER-ON

TOL

DGND

TER

Nonvolatile memory1 stores wiper setting w/write protection

REFRESH

B1

WP

DATA

Power-on refreshed with EEMEM settings in 300 μs typ

SCL

RDAC3

A3

I2C

RDAC3

EEMEM rewrite time = 540 μs typ

SDA

REGIS-

W3

SERIAL

CONTROL

TER

B3

Resistance tolerance stored in nonvolatile memory

AD0

INTERFACE

COMMAND

12 extra bytes in EEMEM for user-defined information

AD1

DECODE LOGIC

I2C-compatible serial interface

ADDRESS

AD5251/

Direct read/write access of RDAC2 and EEMEM registers

POWER-

DECODE LOGIC

AD5252

Predefined linear increment/decrement commands

ON RESET

CONTROL LOGIC

03823-0-001

Predefined ±6 dB step change commands

Figure 1.

Synchronous or asynchronous dual-channel update

Wiper setting readback

4 MHz bandwidth—1 kΩ version

The AD5251/AD5252 allow the host I2C controllers to write

Single supply 2.7 V to 5.5 V

Dual supply ±2.25 V to ±2.75 V

any of the 64-/256-step wiper settings in the RDAC registers

2 slave address decoding bits allow operation of 4 devices

and store them in the EEMEM. Once the settings are stored,

100-year typical data retention, TA = 55°C

they are restored automatically to t e RDAC registers at system

Operating temperature: –40°C to +85°C

power-on; the settings can also be restored dynamically.

APPLICATIONS

The AD5251/AD5252 provide additional increment,

MacshbM

Mechanical potentiometer replacement

decrement, +6 dB step change, and –6 dB step change in

synchronous or asynchronous channel update mode. The

General-purpose DAC replacement

increment and decrement functions allow stepwise linear

LCD panel VCOM adjustment

adjustments, with a ± 6 dB step change equivalent to doubling

White LED brightness adjustment

or halving the RDAC wiper setting. These functions are useful

RF base station power amp bias control

for steep-slope, nonlinear adjustments, such as white LED

Programmable gain and offset control

brightness and audio volume control.

Programmable voltage-to-current conversion

Programmable power supply

The AD5251/AD5252 have a patented resistance-tolerance

Sensor calibrations

storing function that allows the user to access the EEMEM and

GENERAL DESCRIPTION

obtain the absolute end-to-end resistance values of the RDACs

for precision applications.

The AD5251/AD5252 are dual-channel, I2C, nonvolatile mem-

The AD5251/AD5252 are available in TSSOP-14 packages in

ory, digitally controlled potentiometers with 64/256 positions,

1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ options. All parts are

respectively. These devices perform the same electronic adjust-

guaranteed to operate over the –40°C to +85°C extended

ment functions as mechanical potentiometers, trimmers, and

industrial temperature range.

variable resistors. The parts’ versatile programmability allows

multiple modes of operation, including read/write access in the

RDAC and EEMEM registers, increment/decrement of resistance,

resistance changes in ±6 dB scales, wiper setting readback, and

extra EEMEM for storing user-defined information, such as

memory data for other components, look-up table, or system

1 The terms nonvolatile memory and EEMEM are used interchangeably.

identification information.

2 The terms digital potentiometer and RDAC are used interchangeably.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: [phone]	www.analog.com
Fax: [phone]	© 2005 Analog Devices, Inc. All rights reserved.

AD5251/AD5252

TABLE OF CONTENTS

Features ..............................................................................................		1	Theory of Operation ......................................................................	21
Applications.......................................................................................		1	Linear Increment/Decrement Commands .............................	21
General Description .........................................................................		1	±6 dB Adjustments (Doubling/Halving Wiper Setting) .......	21
Functional Block Diagram ..............................................................		1	Digital Input/Output Configuration........................................	22
Revision History ...............................................................................		2	Multiple Devices on One Bus ...................................................	22
Electrical Characteristics .................................................................		3	Terminal Voltage Operation Range .........................................	22
1 kΩ Version..................................................................................		3	Power-Up and Power-Down Sequences..................................	22
10 kΩ, 50 kΩ, 100 kΩ Versions ..................................................		5	Layout and Power Supply Biasing ............................................	23
Interface Timing Characteristics................................................		7	Digital Potentiometer Operation .............................................	23
Absolute Maximum Ratings............................................................		8	Programmable Rheostat Operation.........................................	23
ESD Caution..................................................................................		8	Programmable Potentiometer Operation ...............................	24
Pin Configuration and Function Descriptions.............................		9	Applications.....................................................................................	25
Typical Performance Characteristics ...........................................		10	LCD Panel VCOM Adjustment....................................................	25
I2C Interface.....................................................................................		14	Current-Sensing Amplifier .......................................................	25
I C Interface Detail Description MacshbM
I2C Interface General Description............................................		14	Adjustable High Power LED Driver ........................................	25
2		15	Outline Dimensions	26
...............................................
I2C-Compatible 2-Wire Serial Bus ...........................................		20	Ordering Guide ..........................................................................	27
REVISION HISTORY
9/05—Rev. 0 to Rev. A
Updated Format..................................................................	Universal
Change to Figure 6 .........................................................................		10
Changes to Figure 28......................................................................		15
Changes to Figure 29......................................................................		17
Changes to RDAC/EEMEM Quick Commands Section ..........		18
Changes to EEMEM Write Protection Section...........................		18
Changes to Figure 37......................................................................		22
Deleted Table 13 and Table 14 ......................................................		23
Change to Figure 42 .......................................................................		24
Change to Figure 46 .......................................................................		25
Changes to Ordering Guide ..........................................................		27

6/04—Revision 0: Initial Version

Rev. A | Page 2 of 28

AD5251/AD5252

ELECTRICAL CHARACTERISTICS

1 kΩ VERSION

VDD = 3 V ± 10% or 5 V ± 10%, VSS = 0 V or VDD/VSS = ±2.5 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +85°C, unless otherwise noted.

Table 1.

Parameter	Symbol	Conditions	Min	Typ1	Max	Unit
DC CHARACTERISTICS—
RHEOSTAT MODE
Resolution	N	AD5251			6	Bits
		AD5252			8	Bits
Resistor Differential Nonlinearity2	R-DNL	RWB, RWA = NC, VDD = 5.5 V, AD5251	–0.5	±0.2	+0.5	LSB
		RWB, RWA = NC, VDD = 5.5 V, AD5252	–1.00	±0.25	+1.00	LSB
		RWB, RWA = NC, VDD = 2.7 V, AD5251	–0.75	±0.30	+0.75	LSB
		RWB, RWA = NC, VDD = 2.7 V, AD5252	–1.5	±0.3	+1.5	LSB
Resistor Nonlinearity2	R-INL	RWB, RWA = NC, VDD = 5.5 V, AD5251	–0.5	±0.2	+0.5	LSB
		RWB, RWA = NC, VDD = 5.5 V, AD5252	–2.0	±0.5	+2.0	LSB
		RWB, RWA = NC, VDD = 2.7 V, AD5251	–1.0	+2.5	+4.0	LSB
		RWB, RWA = NC, VDD = 2.7 V, AD5252	–2	+9	+14	LSB
Nominal Resistor Tolerance	ΔRAB/RAB	TA = 25°C	–30		+30	%
Resistance Temperature Coefficient	(ΔRAB/RAB) × 106/ΔT			650		ppm/°C
Wiper Resistance	RW	IW = 1 V/R, VDD = 5 V		75	130	Ω
		IW = 1 V/R, VDD = 3 V		200	300	Ω
Channel-Resistance Matching	ΔRAB1/ΔRAB3			0.15		%
DC CHARACTERISTICS—		MacshbM
3
POTENTIOMETER DIVIDER MODE
Differential Nonlinearity3	DNL	AD5251	–0.5	±0.1	+0.5	LSB
		AD5252	–1.00	±0.25	+1.00	LSB
Integral Nonlinearity	INL	AD5251	–0.5	±0.2	+0.5	LSB
		AD5252	–2.0	±0.5	+2.0	LSB
Voltage Divider Tempco	(ΔVW/VW) × 106/ΔT	Code = half scale		25		ppm/°C
Full-Scale Error	VWFSE	Code = full scale, VDD = 5.5 V, AD5251	–5	–3	0	LSB
		Code = full scale, VDD = 5.5 V, AD5252	–16	–11	0	LSB
		Code = full scale, VDD = 2.7 V, AD5251	−6	–4	0	LSB
		Code = full scale, VDD = 2.7 V, AD5252	–23	–16	0	LSB
Zero-Scale Error	VWZSE	Code = zero scale, VDD = 5.5 V, AD5251	0	3	5	LSB
		Code = zero scale, VDD = 5.5 V, AD5252	0	11	16	LSB
		Code = zero scale, VDD = 2.7 V, AD5251	0	4	6	LSB
		Code = zero scale, VDD = 2.7 V, AD5252	0	15	20	LSB
RESISTOR TERMINALS
Voltage Range4	VA, VB, VW		VSS		VDD	V
Capacitance5 A, B	CA, CB	f = 1 kHz, measured to GND,		85		pF
		code = half scale
Capacitance5 W	CW	f = 1 kHz, measured to GND,		95		pF
		code = half scale
Common-Mode Leakage Current	ICM	VA = VB = VDD/2		0.01	1	μA

Rev. A | Page 3 of 28

AD5251/AD5252

Parameter			Symbol		Conditions		Min	Typ1	Max	Unit
DIGITAL INPUTS AND OUTPUTS
	Input Logic High		VIH		VDD = 5 V, VSS = 0 V		2.4			V
					VDD/VSS = 2.7 V/0 V or VDD/VSS = ± 2.5 V		2.1			V
	Input Logic Low		VIL		VDD = 5 V, VSS = 0 V				0.8	V
	Output Logic High (SDA)		VOH		RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V		4.9			V
	Output Logic Low (SDA)		VOL		RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V				0.4	V
			IWP			= VDD			5	μA
	WP	Leakage Current			WP
	A0 Leakage Current		IA0		A0 = GND				3	μA
	Input Leakage Current		II		VIN = 0 V or VDD				±1	μA
	(Other than WP and A0)
	Input Capacitance5		CI					5		pF
POWER SUPPLIES
	Single-Supply Power Range		VDD		VSS = 0 V		2.7		5.5	V
	Dual-Supply Power Range		VDD/VSS				±2.25		±2.75	V
	Positive Supply Current		IDD		VIH = VDD or VIL = GND			5	15	μA
	Negative Supply Current		ISS		VIH = VDD or VIL = GND, VDD = 2.5 V,			–5	–15	μA
					VSS = –2.5 V
	EEMEM Data Storing Mode Current		IDD_STORE		VIH = VDD or VIL = GND			35		mA
	EEMEM Data Restoring Mode		IDD_RESTORE		VIH = VDD or VIL = GND			2.5		mA
	Current6
	Power Dissipation7		PDISS		VIH = VDD = 5 V or VIL = GND				0.075	mW
	Power Supply Sensitivity		PSS		ΔVDD = 5 V ± 10%		−0.025	+0.010	+0.025	%/%
					ΔVDD = 3 V ± 10%		–0.04	+0.02	+0.04	%/%
DYNAMIC CHARACTERISTICS5, 8
	Bandwidth –3 dB		BW		RAB = 1 kΩ			4		MHz
	Total Harmonic Distortion		THD	VA = 1 V rms, VB = 0 V, f = 1 kHz				0.05		%
	VW Settling Time		tS	MacshbMVA = VDD, VB = 0 V 0.2						μs
	Resistor Noise Voltage		eN_WB		RWB = 500 Ω, f = 1 kHz			3		nV/√Hz
					(thermal noise only)
	Digital Crosstalk		CT		VA = VDD, VB = 0 V, measure VW with			–80		dB
					adjacent RDAC making full-scale
					change
	Analog Coupling		CAT		Signal input at A1 and measure the			–72		dB
					output at W3, f = 1 kHz

1 Typical values represent average readings at 25°C and VDD = 5 V.

2Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ version at VDD =

2.7 V, IW = VDD/R for both VDD = 3 V and VDD = 5 V.

3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

4 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test.

6 Command 0 NOP should be activated after Command 1 to minimize IDD_READ current consumption. 7 PDISS is calculated from IDD × VDD = 5 V.

8 All dynamic characteristics use VDD = 5 V.

Rev. A | Page 4 of 28

AD5251/AD5252

10 kΩ, 50 kΩ, 100 kΩ VERSIONS

VDD = +3 V ± 10% or +5 V ± 10%, VSS = 0 V or VDD/VSS = ± 2.5 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +85°C, unless otherwise noted.

Table 2.

Parameter			Symbol		Conditions		Min	Typ1	Max	Unit
DC CHARACTERISTICS—
	RHEOSTAT MODE
	Resolution		N		AD5251				6	Bits
					AD5252				8	Bits
	Resistor Differential		R-DNL		RWB, RWA = NC, AD5251		−0.75	±0.10	+0.75	LSB
	Nonlinearity2
					RWB, RWA = NC, AD5252		−1.00	±0.25	+1.00	LSB
	Resistor Nonlinearity2		R-INL		RWB, RWA = NC, AD5251		−0.75	±0.25	+0.75	LSB
					RWB, RWA = NC, AD5252		−2.5	±1.0	+2.5	LSB
	Nominal Resistor Tolerance		ΔRAB/RAB		TA = 25°C		−20		+20	%
	Resistance Temperature		(ΔRAB/RAB) × 106/ΔT					650		ppm/°C
	Coefficient
	Wiper Resistance		RW		IW = 1 V/R, VDD = 5 V			75	130	Ω
					IW = 1 V/R, VDD = 3 V			200	300	Ω
	Channel-Resistance Matching		ΔRAB1/ΔRAB2		RAB = 10 kΩ, 50 kΩ			0.15		%
					RAB = 100 kΩ			0.05		%
DC CHARACTERISTICS—
	POTENTIOMETER DIVIDER MODE
	Differential Nonlinearity3		DNL	AD5251			−0.5	±0.1	+0.5	LSB
					AD5252		−1.0	±0.3	+1.0	LSB
	Integral Nonlinearity3		INL	AD5251			−0.50	±0.15	+0.50	LSB
					AD5252		−1.5	±0.5	+1.5	LSB
	Voltage Divider		(ΔVW/VW) × 106/ΔT		Code = lf sc le			15		ppm/°C
	Temperature Coefficient			MacshbM
	Full-Scale Error		VWFSE		Code = full scale, AD5251		−1.0	−0.3	0	LSB
					Code = full scale, AD5252		−3	−1	0	LSB
	Zero-Scale Error		VWZSE		Code = zero scale, AD5251		0	0.3	1.0	LSB
					Code = zero scale, AD5252		0	1.2	3.0	LSB
RESISTOR TERMINALS
	Voltage Range4		VA, VB, VW				VSS		VDD	V
	Capacitance5 A, B		CA, CB		f = 1 kHz, measured to GND,			85		pF
					code = half scale
	Capacitance5 W		CW		f = 1 kHz, measured to GND,			95		pF
					code = half scale
	Common-Mode Leakage Current		ICM		VA = VB = VDD/2			0.01	1.00	μA
DIGITAL INPUTS AND OUTPUTS
	Input Logic High		VIH		VDD = 5 V, VSS = 0 V		2.4			V
					VDD/VSS = +2.7 V/0 V or VDD/VSS = ±2.5 V		2.1			V
	Input Logic Low		VIL		VDD = 5 V, VSS = 0 V				0.8	V
					VDD/VSS = +2.7 V/0 V or VDD/VSS = ±2.5 V				0.6	V
	Output Logic High (SDA)		VOH		RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V		4.9			V
	Output Logic Low (SDA)		VOL		RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V				0.4	V
			IWP			= VDD			5	μA
	WP	Leakage Current			WP
	A0 Leakage Current		IA0		A0 = GND				3	μA
	Input Leakage Current		II		VIN = 0 V or VDD				±1	μA
	(Other than WP and A0)
	Input Capacitance5		CI					5		pF

Rev. A | Page 5 of 28

AD5251/AD5252

Parameter			Symbol	Conditions	Min	Typ1	Max	Unit
POWER SUPPLIES
	Single-Supply Power Range		VDD	VSS = 0 V	2.7		5.5	V
	Dual-Supply Power Range		VDD/VSS		±2.25		±2.75	V
	Positive Supply Current		IDD	VIH = VDD or VIL = GND		5	15	μA
	Negative Supply Current		ISS	VIH = VDD or VIL = GND, VDD = 2.5 V,		−5	−15	μA
				VSS = −2.5 V
	EEMEM Data Storing Mode		IDD_STORE	VIH = VDD or VIL = GND, TA = 0°C to 85°C		35		mA
	Current
	EEMEM Data Restoring Mode		IDD_RESTORE	VIH = VDD or VIL = GND, TA = 0°C to 85°C		2.5		mA
	Current6
	Power Dissipation7		PDISS	VIH = VDD = 5 V or VIL = GND			0.075	mW
	Power Supply Sensitivity		PSS	ΔVDD = 5 V ± 10%	−0.005	+0.002	+0.005	%/%
				ΔVDD = 3 V ± 10%	−0.010	+0.002	+0.010	%/%
DYNAMIC CHARACTERISTICS5, 8
	–3 dB Bandwidth		BW	RAB = 10 kΩ/50 kΩ/100 kΩ		400/80/40		kHz
	Total Harmonic Distortion		THDW	VA = 1 V rms, VB = 0 V, f = 1 kHz		0.05		%
	VW Settling Time		tS	VA = VDD, VB = 0 V,		1.5/7/14		μs
				RAB = 10 kΩ/50 kΩ/100 kΩ
	Resistor Noise Voltage		eN_WB	RAB = 10 kΩ/50 kΩ/100 kΩ,		9/20/29
								nV/√Hz
				code = midscale, f = 1 kHz
				(thermal noise only)
	Digital Crosstalk		CT	VA = VDD, VB = 0 V, measure VW with		−80		dB
				adjacent RDAC making full-scale
				change
	Analog Coupling		CAT	Signal input t A1 nd measure		−72		dB
	nonlinearity error (R-INL)	is the deviation from an		MacshbMideal value measured between the maximum and minimum resistance wiper positions. R				-DNL is the
				output t W3, f = 1 kHz
1 Typical values represent average readings at 25°C and VDD = 5 V.
2	Resistor position
	relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ version at VDD = 2.7 V,
	IW = VDD/R for both VDD = 3 V and VDD = 5 V.

3INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

4 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test.

6 Command 0 NOP should be activated after Command 1 to minimize IDD_READ current consumption. 7 PDISS is calculated from IDD × VDD = 5 V.

8 All dynamic characteristics use VDD = 5 V.

Rev. A | Page 6 of 28

AD5251/AD5252

INTERFACE TIMING CHARACTERISTICS

All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and 5 V.

Table 3. Interface Timing and EEMEM Reliability Characteristics (All Parts)1

Parameter	Symbol		Conditions	Min	Typ Max	Unit
INTERFACE TIMING
SCL Clock Frequency	fSCL				400	kHz
tBUF Bus-Free Time Between Stop and Start	t1			1.3		μs
tHD;STA Hold Time (Repeated Start)	t2		After this period, the first clock pulse is	0.6		μs
			generated.
tLOW Low Period of SCL Clock	t3			1.3		μs
tHIGH High Period of SCL Clock	t4			0.6		μs
tSU;STA Set-up Time for Start Condition	t5			0.6		μs
tHD;DAT Data Hold Time	t6			0	0.9	μs
tSU;DAT Data Set-up Time	t7			100		ns
tF Fall Time of Both SDA and SCL Signals	t8				300	ns
tR Rise Time of Both SDA and SCL Signals	t9				300	ns
tSU;STO Set-up Time for Stop Condition	t10			0.6		μs
EEMEM Data Storing Time	tEEMEM_STORE				26	ms
EEMEM Data Restoring Time at Power-On2	tEEMEM_RESTORE1		VDD rise time dependent. Measure		300	μs
			without decoupling capacitors at VDD
			and VSS.
EEMEM Data Restoring Time upon Restore	tEE	EM RESTORE2	VDD = 5 V.		300	μs
			MacshbM
Command or Reset Operation2
EEMEM Data Rewritable Time (Delay Time	tEE	EM REWRITE			540	μs
After Power-On or Reset Before EEMEM
Can Be Written)
FLASH/EE MEMORY RELIABILITY
Endurance3				100		k cycles
Data Retention4					100	Years

1 Guaranteed by design; not subject to production test. See Figure 23 for location of measured values.

2 During power-up, all outputs are preset to midscale before restoring the EEMEM contents. RDAC0 has the shortest EEMEM data restoring time, whereas RDAC3 has the longest.

3 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.

4Retention lifetime equivalent at junction temperature TJ = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates with junction temperature in Flash/EE memory.

Rev. A | Page 7 of 28

AD5251/AD5252

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter	Rating
VDD to GND	−0.3 V, +7 V
VSS to GND	+0.3 V, −7 V
VDD to VSS	7 V
VA, VB, VW to GND	VSS, VDD
Maximum Current
IWB, IWA Pulsed	±20 mA
IWB Continuous (RWB ≤ 1 kΩ, A Open)1	±5 mA
IWA Continuous (RWA ≤ 1 kΩ, B Open)1	±5 mA
IAB Continuous	±5 mA/±500 μA/
(RAB = 1 kΩ/10 kΩ/50 kΩ/100 kΩ)1	±100 μA/±50 μA
Digital Inputs and Output Voltage to GND	0 V, 7 V
Operating Temperature Range	−40°C to +85°C
Maximum Junction Temperature (TJMAX)	150°C
Storage Temperature Range	−65°C to +150°C
Lead Temperature (Soldering, 10 sec)	300°C
Vapor Phase (60 sec)	215°C
Infrared (15 sec)	220°C
TSSOP-14 Thermal Resistance2 θJA	136°C/W

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

1 Maximum terminal current is bound by the maximum applied voltageMacshbMacross any two of the A, B, and W terminals at a given resistance, the maximum

current handling of the switches, and the maximum power dissipation of the package. VDD = 5 V.

2 Package power dissipation = (TJMAX − TA)/θJA.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 8 of 28

AD5251/AD5252

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VDD			1		14	W3
AD0			2	AD5251/	13	B3
			3		12	A3
	WP
	W1		4	AD5252	11	AD1
				TOP VIEW
	B1		5	(Not to Scale)	10	DGND
	A1		6		9	SCL
SDA			7		8	VSS

Figure 2. Pin Configuration

03823-0-002

Table 5. Pin Function Descriptions

Pin No.		Mnemonic		Description
1		VDD		Positive Power Supply Pin. Connect +2.7 V to +5 V for single supply or ±2.7 V for dual supply, where
				VDD – VSS ≤ 5.5 V. VDD must be able to source 35 mA for 26 ms when storing data to EEMEM.
2		AD0		I2C Device Address 0. AD0 and AD1 allow four AD5251/AD5252 devices to be addressed.
3		WP		Write Protect, Active Low. VWP ≤ VDD + 0.3 V.
4	W1			Wiper Terminal of RDAC1. VSS ≤ VW1 ≤ VDD.1
5	B1			B Terminal of RDAC1. VSS ≤ VB1 ≤ VDD.1
6		A1		A Terminal of RDAC1. VSS ≤ VA1 ≤ VDD.1
7		SDA		Serial Data Input/Output Pin. Shifts in one bit at a time upon positive clock edges. MSB loaded first.
				Open-drain MOSFET requires pull-up resistor.
8		VSS		Negative Supply. Connect to 0 V for single supply or –2.7 V for dual supply, where VDD – VSS ≤ +5.5 V. If
	MacshbM
				VSS is used in dual supply, VSS must be ble to sink 35 mA for 26 ms w en storing data to EEMEM.
9		SCL		Serial Input Register Clock Pin. Shifts in one bit at time upon po itive clock edges. VSCL ≤ (VDD + 0.3 V).
				Pull-up resistor is recommended for SCL to ensure minimum power.
10	DGND			Digital Ground. Connect to system analog ground at a single point.
11		AD1		I2C Device Address 1. AD0 and AD1 allow four AD5251/AD5252 devices to be addressed.
12		A3		A Terminal of RDAC3. VSS ≤ VA3 ≤ VDD.1
13	B3			B Terminal of RDAC3. VSS ≤ VB3 ≤ VDD.1
14	W3			Wiper Terminal of RDAC3. VSS ≤ VW3 ≤ VDD.1

1 For quad-channel device software compatibility, the dual potentiometers in the parts are designated as RDAC1 and RDAC3.

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