Analog Devices AD1893JST, AD1893JN Datasheet

		Low Cost SamplePort
a		16-Bit Stereo Asynchronous
		Sample Rate Converter
		AD1893

FEATURES

Low Cost

TQFP and PDIP Packages

3 V Supply Performance Specified—Very Low Power Automatically Senses Sample Frequencies—No

Programming Required

Rejects Sample Clock Jitter

Accommodates Dynamically Changing Asynchronous Sample Clocks

8 kHz to 56 kHz Sample Clock Frequency Range Approximately 1:2 to 2:1 Ratio Between Sample

Clocks

–96 dB THD+N at 1 kHz

96 dB Dynamic Range

Optimal Clock Tracking Control

Slow/Fast Settling Modes Linear Phase in All Modes Automatic Output Mute

Flexible Four Wire Serial Interfaces with Right-Justified Mode

Power-Down Mode

On-Chip Oscillator

APPLICATIONS

Consumer CD-R, DAT, DCC, MD and 8 mm Video Tape Recorders Including Portables

Digital Audio Communication/Network Systems Computer Multimedia Systems

PRODUCT OVERVIEW

The AD1893 SamplePort® is a fully digital, stereo Asynchronous Sample Rate Converter (ASRC) that solves sample rate interfacing and compatibility problems in digital audio equipment. Conceptually, this converter interpolates the input data up to a very high internal sample rate with a time resolution of 300 ps, then decimates down to the desired output sample rate. The AD1893 is intended for 16-bit low cost, non-varispeed applications where low voltage, low power (i.e., battery-powered) operation is required. Refer to the AD1890/AD1891 data sheet for other products in the SamplePort family. This device is asynchronous because the frequency and phase relationships between the input and output sample clocks (both are inputs to the AD1893 ASRC) are arbitrary and need not be related by a simple integer ratio. There is no need to explicitly select or program the input and output sample clock frequencies, as the AD1893 automatically senses the relationship between the two clocks. The input and output sample clock frequencies can nominally range from 8 kHz to 56 kHz, and the ratio between them can vary from approximately 1:2 to 2:1.

SamplePort is a registered trademark of Analog Devices, Inc.

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

SYSTEM DIAGRAM

EXAMPLE						EXAMPLE
FREQUENCIES:						FREQUENCIES:
DAT 48kHz OR						DAT 48kHz OR
CD 44.1kHz OR			AD1893			CD 44.1kHz OR
BROADCAST 32kHz						BROADCAST 32kHz
INPUT SAMPLE CLOCK					OUTPUT SAMPLE CLOCK
INPUT SERIAL DATA						OUTPUT SERIAL DATA

The AD1893 uses multirate digital signal processing techniques to construct an output sample stream from the input sample stream. The input word width is 4 to 16 bits for the AD1893. Shorter input words are automatically zero-filled in the LSBs. The output word width is 24 bits. The user can receive as many of the output bits as desired. Internal arithmetic is performed with 22-bit coefficients and 27-bit accumulation. The digital samples are processed with unity gain.

The input and output control signals allow for considerable flexibility for interfacing to a variety of DSP chips, AES/EBU receivers and transmitters and for I2S compatible devices. Input and output data can be independently rightor left- (with or without a one bit clock delay) justified to the left/right clock edge. In the right-justified mode, the MSB is delayed 16 bit clock periods from the left/right clock edge transition. Input and output data can also be independently justified to the word clock rising edge. The data justification options are encoded on two mode pins for both the input port and the output port. The bit clocks can also be independently configured for rising edge active or falling edge active operation.

The AD1893 SamplePort ASRC has on-chip digital coefficients that correspond to a highly oversampled 0 Hz to 20 kHz lowpass filter with a flat passband, a very narrow transition band, and a high degree of stopband attenuation. A subset of these filter coefficients are dynamically chosen on the basis of the filtered ratio between the input sample clock (LR I) and the output sample clock (LR 0), and these coefficients are then used in an FIR convolver to perform the sample rate conversion. Refer to the “Theory of Operation” section of this data sheet for a more thorough functional description. The low-pass filter has been designed so that full 20 kHz bandwidth is maintained when the input and output sample clock frequencies are as low as 44.1 kHz. If the output sample rate drops below the input sample rate, the bandwidth of the input signal is automatically

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AD1893–SPECIFICATIONS

TEST CONDITIONS UNLESS OTHERWISE NOTED

Supply Voltage	+3.0	V
Ambient Temperature	25	°C
Crystal Frequency	16	MHz
Load Capacitance	100	pF

All minimums and maximums tested except as noted.

PERFORMANCE† (Guaranteed for VDD = +3.3 V to +5.0 V ± 10%)

						Min	Max	Units
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)						96		dB
Total Harmonic Distortion + Noise								dB
(20 Hz to 20 kHz, Full-Scale Input,
FSOUT/FSIN Between 0.51 and 1.99)							–94	dB
(1 kHz Full-Scale Input, FSOUT/FSIN Between 0.7 and 1.4)							–96	dB
(10 kHz Full-Scale Input, FSOUT/FSIN Between 0.7 and 1.4)							–95	dB
Interchannel Phase Deviation							0	Degrees
Input and Output Sample Clock Jitter						10		ns
(For ≤1 dB Degradation in THD+N with 10 kHz Full-Scale Input, Slow-Settling Mode)
DIGITAL INPUTS (Guaranteed for VDD = +3.0 V to +5.0 V ± 10%)
						Min	Max	Units
VIH	≥ +3.0 V)					2.0		V
VIL (VDD							0.8	V
VIL (+2.7 V ≤ VDD < +3.0 V)							0.7	V
IIH @ VIH = +5.0 V, All Pins Except XTAL_I							4	A
IIH @ VIH = +5.0 V, XTAL_I Pin							6	A
IIL @ VIL = 0 V, All Pins Except XTAL_I							4	A
IIL @ VIL = 0 V, XTAL_I Pin							6	A
VOH @ IOH = –4 mA (VDD ≥ +3.0 V)						2.4		V
VOH @ IOH = –4 mA (+2.7 V ≤ VDD < +3.0 V)						2.2		V
VOL @ IOL = 4 mA							0.4	V
Input Capacitance†							15	pF
DIGITAL TIMING (Guaranteed for VDD = +3.0 V to +5.0 V ± 10%) See Figures 26 through 28.
						Min	Max	Units
tcrystal		Crystal Period				62.5	125	ns
Fcrystal		Crystal Frequency (1/tcrystal)					16	MHz
tPWL		Crystal LO Pulse Width				20		ns
tPWH		Crystal HI Pulse Width				20		ns
FLRI		L	R	_I Frequency with 16 MHz Crystal†		10	56	kHz
tRPWL		RESET LO Pulse Width				125		ns
tRS		RESET			Setup to Crystal Falling	15		ns
tBCLK		BCLK_I/O Period†				120		ns
FBCLK		BCLK_I/O Frequency (l/tBCLK)†					8.33	MHz
tBPWL		BCLK_I/O LO Pulse Width				55		ns
tBPWH		BCLK_I/O HI Pulse Width				55		ns
tWSI		WCLK_I Setup to BCLK_I				15		ns
tWSO		WCLK_O Setup to BCLK_O				40		ns
tLRSI		L	R	_I Setup to BCLK_I		15		ns
tLRSO		LR_O Setup to BCLK_O				55		ns
tDS		Data Setup to BCLK_I				0		ns
tDH		Data Hold from BCLK_I				35		ns
tDPD		Data Propagation Delay from BCLK_O					90	ns
tDOH		Data Output Hold from BCLK_O				15		ns

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						AD1893
DIGITAL FILTER CHARACTERISTICS†
			Min		Max		Units
Passband Ripple (0 to 20 kHz)					0.01		dB
Transition Bandl					4.1		kHz
Stopband Attenuation			110				dB
Group Delay (L		_I = 50 kHz)	700		3000		s
	R
POWER (FSIN = 48 kHz, FSOUT = 44.1 kHz)
			Min	Typ	Max		Units
Supplies
Voltage, VDD			2.7		5.5		V
Operational Current, IDD (VDD = +5.0 V)				30	40		mA
Operational Current, IDD (VDD = +3.0 V)†				15	20		mA
Power-Down Current, IDD (VDD = +5.0 V)				1.5	2.5		mA
Power-Down Current, IDD (VDD = +3.0 V)†				0.5	1.0		mA
Dissipation†
Operation (VDD = +5.0 V)				150	200		mW
Operation (VDD = +3.0 V)				45	60		mW
Power-Down (VDD = +5.0 V)				7.5	12.5		mW
Power-Down (VDD = +3.0 V)				1.5	3.0		mW

TEMPERATURE RANGE

	Min	Max	Units
Operation Guaranteed	–40	+85	°C
Storage	–60	+100	°C
ABSOLUTE MAXIMUM RATINGS*
	Min	Max	Units
VDD to GND	–0.3	7.0	V
DC Input Voltage	–0.3	VDD + 0.3	V
Latch-Up Trigger Current	–1000	+1000	mA
Soldering		+300	°C
		10	sec

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

†Guaranteed, Not Tested

1Valid only when FSOUT ≥ FSIN (i.e., upsampling), FSIN = 44.1 kHz. Specifications subject to change without notice.

ORDERING GUIDE

Model	Temperature Range	Package Description	Package Option
AD1893JN	0°C to +70°C	Plastic DIP	N-28
AD1893JST	0°C to +70°C	TQFP	ST-44

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1893 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

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AD1893

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PRODUCT OVERVIEW (Continued)

limited to avoid alias distortion on the output signal. The AD1893 dynamically alters the low-pass filter cutoff frequency smoothly and slowly, so that real-time variations in the sample rate ratio are possible without degradation of the audio quality.

The AD1893 has a pin selectable slowor fast-settling mode. This mode determines how quickly the ASRC adapts to a change in either the input sample clock frequency (FSIN) or the output sample clock frequency (FSOUT). In the slow-settling mode, the control loop which computes the ratio between FSIN and FSOUT settles in approximately 800 ms and begins to reject jitter above 3 Hz. The slow-settling mode offers the best signal quality and the greatest jitter rejection. In the fast-settling mode, the control loop settles in approximately 200 ms and begins to reject jitter above 12 Hz. The fast-settling mode allows rapid, real time sample rate changes to be tracked without error, at the expense of some narrow-band noise modulation products on the output signal.

The AD1893 features short group delay processing. This feature relates to the depth of the First-In, First-Out (FIFO) memory which buffers the input data samples before they are processed by the FIR convolver. In the AD1893, the group delay is approximately 700 s. If the read and write pointers that manage the FIFO cross (indicating underflow or overflow), the AD1893 asserts the mute output (MUTE_O) pin HI for 128 output clock cycles. If MUTE_O is connected to the mute input (MUTE_I) pin, as it normally should be, the serial output will be muted (i.e., all bits zero) during this transient event.

The AD1893 includes an on-chip oscillator which only requires that the user provide an external crystal. By removing the need for an external oscillator, the AD1893 lowers the total cost of ownership to the end user. The AD1893 also includes a powerdown mode, which is invoked with the PWRDWN pin. Asserting this control signal HI will place the AD1893 into a very low power dissipation in active and standby condition.

The AD1893 is fabricated in a 0.8 m single poly, double metal CMOS process and are packaged in a 0.6" wide 28-pin plastic DIP and a 10 mm by 10 mm body size 44-pin TQFP. The AD1893 operates from a +3 V to +5 V power supply over the temperature range of 0°C to +70°C.

XTAL_O																SETSLW
	1														28
						SERIAL IN
XTAL_I	2														27	PWRDWN
DATA_I	3														26	BCLK_O
								SERIAL OUT								WCLK_O
BCLK_I	4														25
																LR_O
WCLK_I	5														24
								ACCUM
LR_I	6														23	DATA_O
VDD	7														22	VDD
GND	8						MULT								21	GND
N/C	9														20	N/C
																BKPOL_O
BKPOL_I	10		FIFO					COEF ROM							19
MODE0_I	11														18	MODE0_O
MODE1_I	12														17	MODE1_O
																MUTE_O
RESET	13					CLOCK									16
						TRACKING
GND	14														15	MUTE_I

AD1893

N/C = NO CONNECT

AD1893 DIP Pinout

	N/C	I_DATA
	44	43
N/C	1
BCLK_I	2
WCLK_I	3
LR_I	4
N/C	5
VDD	6
GND	7
N/C	8
BKPOL_I	9
MODE0_I 10
N/C	11

IXTAL	N/C	OXTAL	N/C	SETSLW	N/C	PWRDWN	OBCLK	N/C
42	41	40	39	38	37	36	35	34

AD1893

		33	N/C
SERIAL IN	SERIAL OUT	32	WCLK_O
		31	LR_O
ACCUM		30	DATA_O
		29	N/C
MULT		28	VDD
		27	GND
FIFO	COEF ROM	26	N/C
		25	BKPOL_O
CLOCK		24	MODE0_O
TRACKING		23	N/C

12	13	14	15	16	17	18	19	20	21	22
N/C	IMODE1	RESET	N/C	GND	N/C	MUTEI	N/C	MUTEO	MODE10	N/C
N/C = NO CONNECT

AD1893 TQFP Pinout

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DEFINITIONS

Dynamic Range

The ratio of a near full-scale input signal to the integrated noise in the passband (0 to ≈20 kHz), expressed in decibels (dB). Dynamic range is measured with a –60 dB input signal and “60 dB” arithmetically added to the result.

Total Harmonic Distortion + Noise

Total Harmonic Distortion plus Noise (THD+N) is defined as the ratio of the square root of the sum of the squares of the values of the harmonics and noise to the rms value of a sinusoidal input signal. It is usually expressed in percent (%) or decibels.

Interchannel Phase Deviation

Difference in input sampling times between stereo channels, expressed as a phase difference in degrees between 1 kHz inputs.

AD1893 PIN LIST

Serial Input Interface

Group Delay

Intuitively, the time interval required for a full-level input pulse to appear at the converter’s output, at full level, expressed in milliseconds (ms). More precisely, the derivative of radian phase with respect to radian frequency at a given frequency.

Transport Delay

The time interval between when an impulse is applied to the converter’s input and when the output starts to be affected by this impulse, expressed in milliseconds (ms). Transport delay is independent of frequency.

Pin Name

DIP

TQFP

I/O

Description

DATA_I

3

43

I

Serial input, MSB first, containing two channels of 4 to 16 bits of twos-complement data per

channel.

BCLK_I

4

2

I

Bit clock input for input data. Need not run continuously; may be gated or used in a burst fashion.

WCLK_I

5

3

I

Word clock input for input data. This input is rising edge sensitive. (Not required in L

input

R

data clock triggered modes.)

L

_I

6

4

I

Left/

clock input for input data. Must run continuously.

R

right

Serial Output Interface

Pin Name

DIP

TQFP

I/O

Description

DATA_O

23

30

O

Serial output, MSB first, containing two channels of 4- to 24-bits of twos-complement data per

channel.

BCLK_O

26

35

I

Bit clock input for output data. Need not run continuously; may be gated or used in a burst

fashion.

WCLK_O

25

32

I

Word clock input for output data. This input is rising edge sensitive. (Not required in L

output

R

data clock triggered modes.)

L

_O

24

31

I

Left/

clock input for output data. Must run continuously.

R

right

Input Control Signals

Pin Name

DIP

TQFP

I/O

Description

BKPOL_I

10

9

I

Bit clock polarity. LO: Normal mode. Input data is sampled on rising edges of BCLK_I. HI:

Inverted mode. Input data is sampled on falling edges of BCLK_I.

MODE0_I

11

10

I

Serial mode zero control for input port.

MODE1_I

12

13

I

Serial mode one control for input port.

MODE0_I MODE1_I

0

0

Left-justified, no MSB delay, L

_I clock triggered.

R

0

1

Left-justified, MSB delay, L

_I clock triggered.

R

1

0

Right-justified, MSB delayed 16 bit clock periods from L

_I transition.

R

1

1

WCLK_I triggered, no MSB delay.

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AD1893

Output Control Signals

Pin Name

DIP

I/O

TQFP

Description

BKPOL_O

19

I

25

Bit clock polarity. LO: Normal mode. Output data is valid on rising edges of BCLK_O, changed

on falling. HI: Inverted mode. Output data is valid on falling edges of BCLK_O, changed on

rising.

MODE0_O

18

I

24

Serial mode zero control for output port.

MODE1_O

17

I

21

Serial mode one control for output port.

MODE0_O MODE1_O

0

0

Left-justified, no MSB delay, L

_O clock triggered.

R

0

1

Left-justified, MSB delay, L

_O clock triggered.

R

1

0

Right-justified, MSB delayed 16 bit clock periods from L

_O transition.

R

1

1

WCLK_O triggered, no MSB delay.

Miscellaneous

Pin Name

DIP

TQFP

I/O

Description

XTAL_O

1

40

O

Crystal output. Connect to one side of nominal 16 MHz crystal for sampling frequencies

(FS word rates) from 8 kHz to 56 kHz.

XTAL_I

2

42

I

Crystal input. Connect to other side of nominal 16 MHz crystal for sampling frequencies

(FS word rates) from 8 kHz to 56 kHz. Use this input to overdrive the on-chip oscillator

with an external clock source.

13

14

I

Active LO reset. Set HI for normal chip operation.

RESET

MUTE_O

16

20

O

Mute output. HI indicates that data is not currently valid due to read and write FIFO

memory pointer overlap. LO indicates normal operation.

MUTE_I

15

18

I

Mute input. HI mutes the serial output to zeros (midscale). Normally connected to

MUTE_O. Reset LO for normal operation.

SETLSLW

28

38

I

Settle slowly to changes in sample rates. HI: Slow-settling mode (≈800 ms). Less sensitive

to sample clock jitter. LO: Fast-settling mode (≈200 ms). Some narrow-band noise

modulation may result from jitter on the L

R

clocks. This signal may be asynchronous with

respect to the crystal frequency, and dynamically changed, but is normally pulled up or

pulled down on a static basis.

PWRDWN

27

36

I

Power-down input. Set HI for inactive, low power dissipation state. Reset LO for normal

operation.

N/C

9, 20

1, 5, 8,

No connect. Reserved. Do not connect.

11, 12, 15,

17, 19, 22,

23, 26, 29,

33, 34, 37,

39, 41, 44

Power Supply Connections

Pin Name

DIP

I/O

TQFP

Description

VDD

7, 22

I

6, 28

Positive digital voltage supply.

GND

8, 14, 21

I

7, 16, 27

Digital ground. Pin 14 (DIP) and Pin 16 (TQFP) need not be decoupled.

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