Analog Devices AD5516ABC-3, AD5516ABC-2, AD5516ABC-1 Datasheet

a		16-Channel, 12-Bit Voltage-Output DAC
			with 14-Bit Increment Mode
			AD5516*
	FEATURES		GENERAL DESCRIPTION
	High Integration:		The AD5516 is a 16-channel, 12-bit voltage-output DAC. The
	16-Channel DAC in 12 mm 12 mm LFBGA		selected DAC register is written to via the 3-wire serial interface.
	14-Bit Resolution via Increment/Decrement Mode		DAC selection is accomplished via address bits A3–A0. 14-bit
	Guaranteed Monotonic		resolution can be achieved by fine adjustment in Increment/
	Low Power, SPITM, QSPITM, MICROWIRETM, and DSP-		Decrement Mode (Mode 2). The serial interface operates at
	Compatible		clock rates up to 20 MHz and is compatible with standard SPI,
	3-Wire Serial Interface		MICROWIRE, and DSP interface standards. The output volt-
	Output Impedance 0.5		age range is fixed at ±2.5 V (AD5516-1), ±5 V (AD5516-2),
	Output Voltage Range		and ±10 V (AD5516-3). Access to the feedback resistor in each
	2.5 V (AD5516-1)		channel is provided via RFB0 to RFB15 pins.
	5 V (AD5516-2)		The device is operated with AVCC = 5 V ± 5%, DVCC = 2.7 V to
	10 V (AD5516-3)		5.25 V, VSS = –4.75 V to –12 V, and VDD = +4.75 V to +12 V
	Asynchronous Reset-Facility (via RESET Pin)
			and requires a stable 3 V reference on REF_IN.
	Asynchronous Power-Down Facility (via PD Pin)
	Daisy-Chain Mode		PRODUCT HIGHLIGHTS
	Temperature Range: –40 C to +85 C
			1. Sixteen 12-bit DACs in one package, guaranteed monotonic
	APPLICATIONS		2. Available in a 74-lead LFBGA package with a body size of

Level Setting	12 mm 12 mm
Instrumentation
Automatic Test Equipment
Optical Networks
Industrial Control Systems
Data Acquisition
Low Cost I/O	FUNCTIONAL BLOCK DIAGRAM

	DVCC	AVCC	REF_IN	VDD	VSS
				VBIAS	ROFFS	RFB
	AD5516					RFB0
			DAC			VOUT0
RESET					ROFFS	RFB
						RFB1
BUSY		ANALOG				VOUT1
			DAC
	CALIBRATION
		LOOP			ROFFS	RFB
DACGND						RFB14
AGND			DAC			VOUT14
		BUS
DGND					ROFFS	RFB
	MODE1
						RFB15
		12BIT-	DAC			VOUT15
DCEN	INTERFACE		MODE2
		CONTROL		POWER-DOWN
			7-BIT BUS
		LOGIC		LOGIC

SCLK DIN DOUT SYNC

PD

*Protected by U.S. Patent No. 5,969,657; other patents pending SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corporation.

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: [phone]	www.analog.com
Fax: [phone]	© Analog Devices, Inc., 2002

AD5516–SPECIFICATIONS (VDD = +4.75 V to +13.2 V, VSS = –4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DACGND = 0 V; REF_IN = 3 V; All outputs unloaded.

All specifications TMIN to TMAX unless otherwise noted.)

Parameter1	A Version2	Unit	Conditions/Comments
DAC DC PERFORMANCE
Resolution	12	Bits
Integral Nonlinearity (INL)	±2	LSB max	Mode 1
Differential Nonlinearity (DNL)	–1/+1.3	LSB max	±0.5 LSB typ, Monotonic; Mode 1
Increment/Decrement Step-Size	±0.25	LSB typ	Monotonic; Mode 2 Only
Bipolar Zero Error	±7	LSB max
Positive Full-Scale Error	±10	LSB max
Negative Full-Scale Error	±10	LSB max
VOLTAGE REFERENCE
REF_IN
Nominal Input Voltage	3	V
Input Voltage Range3	2.875/3.125	V min/max
Input Current	±1	µA max	< 1 nA typ
ANALOG OUTPUTS (VOUT 0–15)		ppm/°C typ
Output Temperature Coefficient3, 4	10		of FSR
DC Output Impedance3	0.5	Ω typ
Output Range5	±2.5
AD5516-1		V typ
AD5516-2	±5	V typ
AD5516-3	±10	V typ
Resistive Load3, 6	5	kΩ min
Capacitive Load3, 6	200	pF
Short-Circuit Current3	7	mA typ	VDD = +12 V ± 5%, VSS = –12 V ± 5%
DC Power-Supply Rejection Ratio3	–85	dB typ
DC Crosstalk3	120	µV max
DIGITAL INPUTS3	±10	µA max	±5 µA typ
Input Current
Input Low Voltage	0.8	V max	DVCC = 5 V ± 5%
	0.4	V max	DVCC = 3 V ± 10%
Input High Voltage	2.4	V min	DVCC = 5 V ± 5%
	2	V min	DVCC = 3 V ± 10%
Input Hysteresis (SCLK and SYNC)	150	mV typ
Input Capacitance	10	pF max	5 pF typ
DIGITAL OUTPUTS (BUSY, DOUT)3			Sinking 200 µA
Output Low Voltage, DVCC = 5 V	0.4	V max
Output High Voltage, DVCC = 5 V	4	V min	Sourcing 200 µA
Output Low Voltage, DVCC = 3 V	0.4	V max	Sinking 200 µA
Output High Voltage, DVCC = 3 V	2.4	V min	Sourcing 200 µA
High Impedance Leakage Current (DOUT only)	±1	µA max	DCEN = 0
High Impedance Output Capacitance (DOUT only)	5	pF typ	DCEN = 0
POWER REQUIREMENTS
Power Supply Voltages
VDD	+4.75/+15.75	V min/max
VSS	–4.75/–15.75	V min/max
AVCC	4.75/5.25	V min/max
DVCC	2.7/5.25	V min/max
Power Supply Currents7
IDD	5	mA max	3.5 mA typ. All Channels Full-Scale
ISS	5	mA max	3.5 mA typ. All Channels Full-Scale
AICC	17	mA max	13 mA typ
DICC	1.5	mA max	1 mA typ
Power-Down Currents7		µA max
IDD	2		200 nA typ
ISS	3	µA max	200 nA typ
AICC	2	µA max	200 nA typ
DICC	2	µA max	200 nA typ
Power Dissipation7	105	mW typ	VDD = +5 V, VSS = –5 V

NOTES

1See Terminology section.

2A Version: Industrial temperature range –40°C to +85°C; typical at +25°C. 3Guaranteed by design and characterization; not production tested. 4AD780 as reference for the AD5516.

5Output range is restricted from VSS + 2 V to VDD – 2 V. Output span varies with reference voltage and is functional down to 2 V.

6Ensure that you do not exceed TJ (MAX). See Absolute Maximum Ratings section. 7Outputs unloaded.

Specifications subject to change without notice.

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AD5516

(VDD = +4.75 V to +13.2 V, VSS = –4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND AC CHARACTERISTICS = DACGND = 0 V; REF_IN = 3 V; All outputs unloaded. All specifications TMIN to TMAX unless otherwise noted.)

Parameter1, 2	A Version3	Unit	Conditions/Comments
Output Voltage Settling Time (Mode 1)4	32	s max	100 pF, 5 kΩ Load Full-Scale Change
Output Voltage Settling Time (Mode 2)4	2.5	s max	100 pF, 5 kΩ Load, 1 Code Increment
Slew Rate	0.85	V/ s typ
Digital-to-Analog Glitch Impulse	1	nV-s typ	1 LSB Change around Major Carry
Digital Crosstalk	5	nV-s typ
Analog Crosstalk AD5516-1	10	nV-s typ
Digital Feedthrough	1	nV-s typ
Output Noise Spectral Density @ 1 kHz	150	nV/(Hz)1/2 typ	AD5516-1

NOTES

1See Terminology section.

2Guaranteed by design and characterization; not production tested. 3A version: Industrial temperature range –40°C to +85°C.

4 Timed from the end of a write sequence.

Specifications subject to change without notice.

TIMING CHARACTERISTICS		(VDD = +4.75 V to +13.2 V, VSS = – 4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V;
		AGND = DGND = DACGND = 0 V. All specifications TMIN to TMAX unless otherwise noted.)
Parameter1, 2, 3	Limit at TMIN, TMAX
	(A Version)		Unit	Conditions/Comments
fUPDATE1	32		kHz max	DAC Update Rate (Mode 1)
fUPDATE2	750		kHz max	DAC Update Rate (Mode 2)
fCLKIN	20		MHz max	SCLK Frequency
t1	20		ns min	SCLK High Pulsewidth
t2	20		ns min	SCLK Low Pulsewidth
t3	15		ns min	SYNC Falling Edge to SCLK Falling Edge Setup Time
t4	5		ns min	DIN Setup Time
t5	5		ns min	DIN Hold Time
t6	0		ns min	SCLK Falling Edge to SYNC Rising Edge
t7	10		ns min	Minimum SYNC High Time (Standalone Mode)
t7MODE2	400		ns min	Minimum SYNC High Time (Daisy-Chain Mode)
t8MODE1	10		ns min	BUSY Rising Edge to SYNC Falling Edge
t9MODE2	200		ns min	18th SCLK Falling Edge to SYNC Falling Edge (Standalone Mode)
t10	10		ns min	SYNC Rising Edge to SCLK Rising Edge (Daisy-Chain Mode)
t114	20		ns max	SCLK Rising Edge to DOUT Valid (Daisy-Chain Mode)
t12	20		ns min	RESET Pulsewidth

NOTES

1See Timing Diagrams in Figures 1 and 2.

2Guaranteed by design and characterization; not production tested.

3All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2. 4This is measured with the load circuit of Figure 3.

Specifications subject to change without notice.

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AD5516

SERIAL INTERFACE TIMING DIAGRAMS

SCLK

1

2

17

18

	t3	t2	t1
	t		t6
	7
SYNC
		t4	t9 MODE2
	MSB	t5	LSB
DIN	BIT 17		BIT 0
	t8 MODE1
BUSY

t12

RESET

Figure 1. Serial Interface Timing Diagram

SCLK
	t3	t2	t1			t10
	t7 MODE2					t6
SYNC
		t4
	MSB	t5		LSB
DIN	BIT 17			BIT 0	BIT 17	BIT 0
		INPUT WORD FOR DEVICE N				INPUT WORD FOR DEVICE N+1
					t11
DOUT					BIT 17	BIT 0
	t8 MODE1	UNDEFINED				INPUT WORD FOR DEVICE N
BUSY

Figure 2. Daisy-Chaining Timing Diagram

	200 A	IOL
	TO OUTPUT	1.6V
	PIN CL
	50pF
	200 A	IOH

Figure 3. Load Circuit for DOUT Timing Specifications

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AD5516

ABSOLUTE MAXIMUM RATINGS1, 2

(TA = 25°C unless otherwise noted.)
VDD to AGND . . . . . . . . . . . . . . . . .	.	. . . . . . –0.3 V to +17 V
VSS to AGND . . . . . . . . . . . . . . . . .	. .	. . . . . +0.3 V to –17 V
AVCC to AGND, DACGND . . . . . .	. .	. . . . . . –0.3 V to +7 V
DVCC to DGND . . . . . . . . . . . . . . .	. .	. . . . . . –0.3 V to +7 V
Digital Inputs to DGND . . . . . . . . .	.	–0.3 V to DVCC + 0.3 V
Digital Outputs to DGND . . . . . . . .	.	–0.3 V to DVCC + 0.3 V
REF_IN to AGND, DACGND . . . .	.	–0.3 V to AVCC + 0.3 V
VOUT 0–15 to AGND . . . . . . . . . . . .	VSS – 0.3 V to VDD + 0.3 V
AGND to DGND . . . . . . . . . . . . . .	. .	. . . . –0.3 V to +0.3 V
RFB 0–15 to AGND . . . . . . . . . . . .	VSS – 0.3 V to VDD + 0.3 V
Operating Temperature Range, Industrial		. . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . .	–65°C to +150°C
Junction Temperature (TJ MAX) . . . . . . . . . .	. . . . . . . .	. 150°C
74-Lead LFBGA Package, JA Thermal Impedance . .		41°C/W
Reflow Soldering		220°C
Peak Temperature . . . . . . . . . . . . . . . . . .	. . . . . . . .
Time at Peak Temperature . . . . . . . . . . . .	.10 sec to 40 sec

NOTES

1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

Model	Function	Output Voltage Span	Package Option
AD5516ABC-1	16 DACs	±2.5 V	74-Lead LFBGA
AD5516ABC-2	16 DACs	±5 V	74-Lead LFBGA
AD5516ABC-3	16 DACs	±10 V	74-Lead LFBGA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5516 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

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