a |
16-Bit Monotonic |
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Voltage Output D/A Converter |
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AD569 |
FEATURES
Guaranteed 16-Bit Monotonicity Monolithic BiMOS II Construction 60.01% Typical Nonlinearity
8- and 16-Bit Bus Compatibility
3 ms Settling to 16 Bits
Low Drift
Low Power
Low Noise
APPLICATIONS
Robotics
Closed-Loop Positioning
High-Resolution ADCs
Microprocessor-Based Process Control
MIL-STD-883 Compliant Versions Available
PRODUCT DESCRIPTION
The AD569 is a monolithic 16-bit digital-to-analog converter (DAC) manufactured in Analog Devices’ BiMOS II process. BiMOS II allows the fabrication of low power CMOS logic functions on the same chip as high precision bipolar linear circuitry. The AD569 chip includes two resistor strings, selector switches decoding logic, buffer amplifiers, and double-buffered input latches.
The AD569’s voltage-segmented architecture insures 16-bit monotonicity over time and temperature. Integral nonlinearity is maintained at ±0.01%, while differential nonlinearity is
±0.0004%. The on-chip, high-speed buffer amplifiers provide a voltage output settling time of 3 μs to within ±0.001% for a full-scale step.
The reference input voltage which determines the output range can be either unipolar or bipolar. Nominal reference range is
±5 V and separate reference force and sense connections are provided for high accuracy applications. The AD569 can operate with an ac reference in multiplying applications.
Data may be loaded into the AD569’s input latches from 8- and 16-bit buses. The double-buffered structure simplifies 8-bit bus interfacing and allows multiple DACs to be loaded asynchronously and updated simultaneously. Four TTL/LSTTL/5 V CMOS-compatible signals control the latches: CS, LBE, HBE, and LDAC
The AD569 is available in five grades: J and K versions are specified from 0°C to +70°C and are packaged in a 28-pin plastic DIP and 28-pin PLCC package; AD and BD versions are specified from –25°C to +85°C and are packaged in a 28-pin ceramic DIP. The SD version, also in a 28-pin ceramic DIP, is specified from –55°C to +125°C.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS
1.Monotonicity to 16 bits is insured by the AD569’s voltagesegmented architecture.
2.The output range is ratiometric to an external reference or ac signal. Gain error and gain drift of the AD569 are negligible.
3.The AD569’s versatile data input structure allows loading from 8- and 16-bit buses.
4. The on-chip output buffer amplifier can supply ±5 V into a 1 kΩ load, and can drive capacitive loads of up to 1000 pF.
5.Kelvin connections to the reference inputs preserve the gain and offset accuracy of the transfer function in the presence of wiring resistances and ground currents.
6.The AD569 is available in versions compliant with MIL-STD-
883.Refer to the Analog Devices Military Products Databook or current AD569/883B data sheet for detailed specifications.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD569–SPECIFICATIONS (TA = +258C, +VS = +12 V, –VS = –12 V, +VREF = +5 V, –VREF = –5 V, unless otherwise noted.)
Model |
AD569JN/JP/AD |
AD569KN/KP/BD |
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AD569SD |
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Parameter |
Min |
Typ |
Max |
Min |
Typ |
Max |
Min |
Typ |
Max |
Units |
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RESOLUTION |
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16 |
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16 |
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16 |
Bits |
LOGIC INPUTS |
2.0 |
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5.5 |
2.0 |
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5.5 |
2.0 |
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5.5 |
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VIH(Logic “l”) |
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Volts |
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VIL (Logic “0”) |
0 |
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0.8 |
0 |
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0.8 |
0 |
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0.8 |
Volts |
IIH (VIH = 5.5 V) |
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10 |
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10 |
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10 |
mA |
IIL (VIL = 0 V) |
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10 |
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10 |
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10 |
mA |
TRANSFER FUNCTION |
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CHARACTERISTICS |
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± 0.02 |
60.04 |
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± 0.01 |
60.024 |
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60.04 |
% FSR1 |
Integral Nonlinearity |
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TMIN to TMAX |
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± 0.02 |
60.04 |
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± 0.020 |
60.024 |
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60.04 |
% FSR |
Differential Nonlinearity |
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± 1/2 |
61 |
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± 1/4 |
61/2 |
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61 |
LSB |
TMIN to TMAX |
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± 1/2 |
61 |
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± 1/2 |
61 |
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61 |
LSB |
Unipolar Offset2 |
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6500 |
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6350 |
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6500 |
mV |
TMIN to TMAX |
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6750 |
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6450 |
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6750 |
mV |
Bipolar Offset2 |
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6500 |
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6350 |
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6500 |
mV |
TMIN to TMAX |
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6750 |
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6450 |
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6750 |
mV |
Full Scale Error2 |
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6350 |
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6350 |
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6350 |
mV |
TMIN to TMAX |
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6750 |
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6750 |
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6750 |
mV |
Bipolar Zero2 |
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60.04 |
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60.024 |
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60.04 |
% FSR |
TMIN to TMAX |
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60.04 |
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60.024 |
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60.04 |
% FSR |
REFERENCE INPUT |
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+VREF Range3 |
–5 |
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+5 |
–5 |
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+5 |
–5 |
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+5 |
Volts |
–VREF Range |
–5 |
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+5 |
–5 |
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+5 |
–5 |
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+5 |
Volts |
Resistance |
15 |
20 |
25 |
15 |
20 |
25 |
15 |
20 |
25 |
kW4 |
OUTPUT CHARACTERISTICS |
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Voltage |
–5 |
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+5 |
–5 |
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+5 |
–5 |
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+5 |
Volts |
Capacitive Load |
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1000 |
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1000 |
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1000 |
pF |
Resistive Load |
1 |
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1 |
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1 |
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kW |
Short Circuit Current |
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10 |
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10 |
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10 |
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mA |
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POWER SUPPLIES |
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Voltage |
+10.8 |
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+13.2 |
+10.8 |
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+13.2 |
+10.8 |
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+13.2 |
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+VS |
+12 |
+12 |
+12 |
Volts |
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–VS |
–10.8 |
–12 |
–13.2 |
–10.8 |
–12 |
–13.2 |
–10.8 |
–12 |
–13.2 |
Volts |
Current |
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+IS |
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+9 |
+13 |
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+9 |
+13 |
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+9 |
+13 |
mA |
–IS |
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–9 |
–13 |
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–9 |
–13 |
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–9 |
–13 |
mA |
Power Supply Sensitivity5 |
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+10.8 V £ +VS £ +13.2 V |
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± 0.5 |
62 |
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± 0.5 |
62 |
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± 0.5 |
62 |
ppm/% |
–10.8 V ³ –VS ³ –13.2 V |
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± 1 |
63 |
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± 1 |
63 |
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± 1 |
63 |
ppm/% |
TEMPERATURE RANGE |
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Specified |
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°C |
JN, KN, JP, KP |
0 |
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+70 |
0 |
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+70 |
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AD, BD |
–25 |
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+85 |
–25 |
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+85 |
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°C |
SD |
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–55 |
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+125 |
°C |
Storage |
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°C |
JN, KN, JP, KP |
–65 |
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+150 |
–65 |
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+150 |
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AD, BD, SD |
–65 |
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+150 |
–65 |
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+150 |
–65 |
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+150 |
°C |
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NOTES
1FSR stands for Full-Scale Range, and is 10 V for a –5 V to +5 V span. 2Refer to Definitions section.
3For operation with supplies other than ± 12 V, refer to the Power Supply and Reference Voltage Range Section. 4Measured between +VREF Force and –VREF Force.
5Sensitivity of Full-Scale Error due to changes in +VS and sensitivity of Offset to changes in –VS.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
–2– |
REV. A |
AD569
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for Design Guidance Only and are not subject to test. +VS = +12 V; –VS = –12 V; +VREF = +5 V; –VREF = –5 V excepts where stated.
Parameter |
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Limit |
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Units |
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Test Conditions/Comments |
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Output Voltage Settling |
5 |
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μs max |
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No Load Applied |
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(Time to ±0.001% FS |
3 |
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μs typ |
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(DAC output measured from falling edge of |
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LDAC |
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For FS Step) |
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6 |
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μs max |
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VOUT Load = 1 kΩ, CLOAD = 1000 pF. |
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4 |
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μs typ |
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(DAC output measured from falling edge of |
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LDAC. |
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Digital-to-Analog Glitch |
500 |
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nV-sec typ |
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Measured with VREF = 0 V. DAC registers alternatively loaded |
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Impulse |
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with input codes of 8000H and 0FFFH (worst-case |
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transition). Load = 1 kΩ. |
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Multiplying Feedthrough |
–100 |
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dB max |
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+VREF = 1 V rms 10 kHz sine wave, |
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–VREF = 0 V |
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Output Noise Voltage |
40 |
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nV/Ï |
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typ |
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Measured between VOUT and –VREF |
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Hz |
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Density (1 kHz-1 MHz) |
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TIMING CHARACTERISTICS (+VS = +12 V, –VS = –12 V, VIH = 2.4 V, VIL = 0.4 V,TMIN to TMAX) |
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Parameter |
Limit |
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Units |
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Test Conditions/Comments |
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Case A |
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150 ns Pulse on |
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, |
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, and |
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HBE |
LBE |
LDAC |
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tWC |
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THS = 140 ns min, THH = 10 ns min |
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120 |
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ns min |
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CS |
Pulse Width |
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tSC |
60 |
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ns min |
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CS |
Data Setup Time |
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tHC |
20 |
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ns min |
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CS Data Hold Time |
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Case B |
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None |
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tWB |
70 |
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ns min |
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, |
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Pulse Width |
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HBE |
LBE |
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tSB |
80 |
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ns min |
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HBE |
, |
LBE |
Data Setup Time |
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tHB |
20 |
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ns min |
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HBE |
, |
LBE |
Data Hold Time |
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tSCS |
120 |
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ns min |
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CS Setup Time |
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tHCS |
10 |
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ns min |
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CS |
Hold Time |
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tWD |
120 |
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ns min |
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LDAC |
Pulse Width |
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Case C |
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None |
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Figure 2a. AD569 Timing Diagram – Case B |
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tWB |
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120 |
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ns min |
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HBE |
, |
LBE |
Pulse Width |
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tSB |
80 |
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ns min |
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HBE |
, |
LBE |
Data Setup Time |
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tHB |
20 |
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ns min |
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HBE, LBE Data Hold Time |
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tSCS |
120 |
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ns min |
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CS |
Setup Time |
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tHCS |
10 |
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ns min |
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CS |
Hold Time |
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Figure 1. AD569 Timing Diagram – Case A |
Figure 2b. AD569 Timing Diagram – Case C |
REV. A |
–3– |
AD569
ABSOLUTE MAXIMUM RATINGS* |
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Power Dissipation (Any Package) . . . . . . . . . |
. . . . . . 1000 mW |
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(TA = +25°C unless otherwise noted) |
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Operating Temperature Range |
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+VS (Pin 1) to GND (Pin 18) . . . . . . |
. . . . . . . |
. +18 V, –0.3 V |
Commercial Plastic (JN, KN, JP, KP Versions) 0°C to +70°C |
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–VS (Pin 28) to GND (Pin 18) . . . . . . . |
. . . . . . . |
–18 V, +0.3 V |
Industrial Ceramic (AD, BD Versions) . . . . –25°C to +85°C |
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+VS (Pin 1) to –VS (Pin 28) . . . . . . . . . |
. . . . . . |
+26.4 V, –0.3 V |
Extended Ceramic (SD Versions) . . . . . . . |
–55°C to +125°C |
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Digital Inputs |
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Storage Temperature . . . . . . . . . . . . . . . . . . . |
–65°C to +150°C |
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(Pins 4-14, 19-27) to GND (Pin 18) |
. . . . . . . |
. . +VS, –0.3 V |
Lead Temperature Range (Soldering, 10 secs) |
. . . . . . . +300°C |
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+VREF Force (Pin 3) to +VREF Sense (Pin 2) . . . |
. . . . . ±16.5 V |
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–VREF Force (Pin 15) to –VREF Sense (Pin 16) . . |
. . . . . ±16.5 V |
*Stresses above those listed under “Absolute Maximum Ratings” may cause |
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VREF Force (Pins 3, 15) to GND (Pin 18) |
±VS |
permanent damage to the device. This is a stress rating only and functional |
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operation of the device at these or any other conditions above those indicated in the |
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VREF Sense (Pins 2, 16) to GND (Pin 18) |
±VS |
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operational sections of this specification is not implied. Exposure to absolute |
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. . . . . . . . . . . . . . . . . .VOUT (Pin 17) |
Indefinite Short to GND |
maximum rating conditions for extended periods may affect device reliability. |
Momentary Short to +VS, –VS
ESD SENSITIVITY |
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The AD569 features input protection circuitry consisting of large “distributed” diodes and polysilicon |
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series resistors to dissipate both high-energy discharges (Human Body Model) and fast, low-energy |
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pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the AD569 has been |
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classified as a Category A device. |
WARNING! |
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Proper ESD precautions are strongly recommended to avoid functional damage or performance |
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degradation. Charges as high as 4000 volts readily accumulate on the human body and test equipment |
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and discharge without detection. Unused devices must be stored in conductive foam or shunts, and |
ESD SENSITIVE DEVICE |
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the foam should be discharged to the destination socket before devices are removed. For further |
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information on ESD precautions, refer to Analog Devices’ ESD Prevention Manual. |
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PIN DESIGNATIONS |
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ORDERING GUIDE
|
Integral Nonlinearity |
Differential Nonlinearity |
Temperature |
Package |
||
Model1 |
+258C |
TMIN–TMAX |
+258C |
TMIN–TMAX |
Range |
Option2 |
AD569JN |
±0.04% |
±0.04% |
±1 LSB |
±1 LSB |
0°C to +70°C |
N-28 |
AD569JP |
±0.04% |
±0.04% |
±1 LSB |
±1 LSB |
0°C to +70°C |
P-28A |
AD569KN |
±0.024% |
±0.024% |
±1/2 LSB |
±1 LSB |
0°C to +70°C |
N-28 |
AD569KP |
±0.024% |
±0.024% |
±1/2 LSB |
±1 LSB |
0°C to +70°C |
P-28A |
AD569AD |
±0.04% |
±0.04% |
±1 LSB |
±1 LSB |
–25°C to +85°C |
D-28 |
AD569BD |
±0.024% |
±0.024% |
±1/2 LSB |
±1 LSB |
–25°C to +85°C |
D-28 |
AD569SD |
±0.04% |
±0.04% |
±1 LSB |
±1 LSB |
–55°C to +125°C |
D-28 |
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NOTES
1For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current AD569/883B data sheet.
2D = Ceramic DIP; N = Plastic DIP; P = Plastic Leaded Chip Carrier.
–4– |
REV. A |