Analog Devices AD2S82ALP, AD2S82AKP, AD2S82AJP, AD2S82AHP Datasheet

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a		Variable Resolution, Monolithic
a		Resolver-to-Digital Converters

		AD2S81A/AD2S82A

FEATURES

Monolithic (BiMOS ll) Tracking R/D Converter Ratiometric Conversion

Low Power Consumption: 300 mW Typ Dynamic Performance Set by User Velocity Output

ESD Class 2 Protection (2,000 V Min)

AD2S81A

28-Lead DIP Package

Low Cost

AD2S82A

44-Lead PLCC Package

10-, 12-, 14and 16-Bit Resolution Set by User High Max Tracking Rate 1040 RPS (10 Bits) VCO Output (Inter LSB Output)

Data Complement Facility Industrial Temperature Range

APPLICATIONS

DC Brushless and AC Motor Control

Process Control

Numerical Control of Machine Tools

Robotics

Axis Control

GENERAL DESCRIPTION

The AD2S82A is a monolithic 10-, 12-, 14or 16-bit tracking resolver-to-digital converter contained in a 44-lead J leaded PLCC package. Two extra functions are provided in the new surface mount package–COMPLEMENT and VCO output.

The AD2S81A is a monolithic 12-bit fixed resolution tracking resolver-to-digital converter packaged in a 28-lead DIP.

The converters allow users to select their own dynamic performance with external components. This allows the users great flexibility in defining the converter that best suits their system requirements. The AD2S82A allows users to select the resolution to be 10, 12, 14 or 16 bits and to track resolver signals rotating at up to 1040 revs per second (62,400 rpm) when set to 10-bit resolution.

The AD2S81A and AD2S82A convert resolver format input signals into a parallel natural binary digital word using a ratiometric tracking conversion method. This ensures high-noise immunity and tolerance of lead length when the converter is remote from the resolver.

The output word is in a three-state digital logic form available in two bytes on the 16 output data lines for the AD2S82A and on

eight output data lines for the AD2S81A. BYTE SELECT, ENABLE and INHIBIT pins ensure easy data transfer to 8- and

16-bit data buses, and outputs are provided to allow for cycle or pitch counting in external counters.

REV. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

AD2S82A FUNCTIONAL BLOCK DIAGRAM

DEMOD DEMOD		INTEGRATOR
I/P	O/P	I/P

	AD2S82A
		PHASE
SIN I/P	A1	SENSITIVE		INTEGRATOR
SIN I/P	A1	DETECTOR		O/P
SIGNAL		SEGMENT		O/P
SIGNAL		SEGMENT
GND		SWITCHING
COS I/P	A2	R-2R	A3	AC ERROR
ANALOG		DAC		O/P
GND
RIPPLE			VCO DATA	VCO I/P
CLK		16-BIT		VCO I/P
CLK
			TRANSFER	INHIBIT
+12V		UP/DOWN COUNTER	TRANSFER	INHIBIT
+12V		UP/DOWN COUNTER	LOGIC	VCO O/P
–12V			LOGIC


COMP		OUTPUT DATA LATCH		+5V
DATA		OUTPUT DATA LATCH		DIGITAL
DATA				DIGITAL
LOAD				GND
	SC2		BUSY DIR

SC1 ENABLE	16 DATA BITS	BYTE
		SELECT

An analog signal proportional to velocity is also available and can be used to replace a tachogenerator.

PRODUCT HIGHLIGHTS

Monolithic. A one-chip solution reduces the package size required and increases the reliability.

Resolution Set by User. Two control pins are used to select the resolution of the AD2S82A to be 10, 12, 14 or 16 bits allowing the user to use the AD2S82A with the optimum resolution for each application.

Ratiometric Tracking Conversion. Conversion technique provides continuous output position data without conversion delay and is insensitive to absolute signal levels. It also provides good noise immunity and tolerance to harmonic distortion on the reference and input signals.

Dynamic Performance Set by the User. By selecting external resistor and capacitor values the user can determine bandwidth, maximum tracking rate and velocity scaling of the converter to match the system requirements. The external components required are all low cost, preferred value resistors and capacitors, and the component values are easy to select using the simple instructions given.

Velocity Output. An analog signal proportional to velocity is available and is linear to typically one percent. This can be used in place of a velocity transducer in many applications to provide loop stabilization in servo controls and velocity feedback data.

Low Power Consumption. Typically only 300 mW.

MODELS AVAILABLE

Information on the models available is given in the Ordering Guide.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700	World Wide Web Site: http://www.analog.com
Fax: 781/326-8703	© Analog Devices, Inc., 1998

AD2S81A/AD2S82A–SPECIFICATIONS (@ TA = +258C, unless otherwise noted)

AD2S81A

AD2S82A

Parameter

Conditions

Min

Typ

Max

Min

Typ

Max

Units

SIGNAL INPUTS

Frequency

400

20,000

Voltage Level

1.8

2.0

2.2

1.8

2.0

2.2

V rms

Input Bias Current

150

Input Impedance

1.0

±8

1.0

±8

MΩ

Maximum Voltage

V pk

REFERENCE INPUT

Frequency

400

20,000

Voltage Level

1.0

8.0

1.0

8.0

V pk

Input Bias Current

150

Input Impedance

1.0

MΩ

CONTROL DYNAMICS

Repeatability

LSB

Allowable Phase Shift

(Signals to Reference)

–10

+10

–10

+10

Degrees

Tracking Rate

10 Bits

1040

rps

12 Bits

260

rps

14 Bits

rps

Bandwidth1

16 Bits

16.25

rps

User Selectable

ACCURACY

622 + 1 LSB

Angular Accuracy

arc min

630 + 1 LSB

68 + 1 LSB

arc min

64 + 1 LSB

arc min

62 + 1 LSB

arc min

Monotonicity

Guaranteed Monotonic

Missing Codes (16-Bit Resolution)

J, K

Codes

Code

VELOCITY SIGNAL

±1

Linearity

Over Full Range

% FSD

Reversion Error

±2

% FSD

DC Zero Offset2

DC Zero Offset Tempco

–22

610

–22

610

µV/°C

Gain Scaling Accuracy

% FSD

Output Voltage

1 mA Load

±8

±9

±10.5

±8

±9

±10.5

Dynamic Ripple

Mean Value

1.5

% rms O/P

Output Load

1.0

kΩ

INPUT/OUTPUT PROTECTION

±8

Analog Inputs

Overvoltage Protection

Analog Outputs

Short Circuit O/P Protection

±5.6

±8

±10.4

±5.6

±8

±10.4

DIGITAL POSITION

Resolution

10, 12, 14 and 16

Output Format

Bidirectional Natural Binary

Load

LSTTL

INHIBIT

Sense

Logic LO to Inhibit

Time to Stable Data

600

Logic LO Enables Position

ENABLE

Output. Logic HI Outputs in

/Disable Time

High Impedance State

110

ENABLE

BYTE SELECT3

Sense

Logic HI

MS Byte DB1–DB8,

(LS Byte DB9–DB16)4

Logic LO

LS Byte DB1–DB8,

Time to Data Available

(LS Byte DB9–DB16)4

140

SHORT CYCLE INPUTS4, 5

Internally Pulled High

SC1

SC2

(100 kΩ) to +VS

10 Bit

12 Bit

14 Bit

16 Bit

DATA LOAD4, 5

Internally Pulled High (100 kΩ)

Sense

150

300

to +VS; Logic LO Allows

Data to Be Loaded into the

Counters from the Data Lines

–2–

REV. B

AD2S81A/AD2S82A

AD2S81A

AD2S82A

Parameter

Conditions

Min Typ

Max

Min Typ

Max

Units

4, 5

Internally Pulled High (100 kΩ) to

COMPLEMENT

+VS; Logic LO to Activate; No

Connect for Normal Operation

BUSY3

Sense

Logic HI When Position O/P Changing

200

600

200

600

Width

Load

Use Additional Pull-Up

LSTTL

DIRECTION3

Sense

Logic HI Counting Up

Max Load

Logic LO Counting Down

LSTTL

RIPPLE CLOCK3

Sense

Logic HI, All 1s to All 0s

All 0s to All 1s

300

Width

Dependent On Input Velocity

Reset

Before Next Busy

Load

LSTTL

DIGITAL INPUTS

2.0

High Voltage, VIH

INHIBIT

ENABLE

DB1–DB16, Byte Select

±VS = ±10.8 V, VL = 5.0 V

0.8

Low Voltage, VIL

INHIBIT,

ENABLE

DB1–DB16, Byte Select

±VS = ±13.2 V, VL = 5.0 V

DIGITAL INPUTS

6100

µA

High Current, IIH

INHIBIT

ENABLE

DB1–DB16

±VS = ±13.2 V, VL = 5.5 V

6100

µA

Low Current, IIL

INHIBIT,

ENABLE

DB1–DB16, Byte Select

±VS = ±13.2 V, VL = 5.5 V

DIGITAL INPUTS

1.0

Low Voltage, VIL

ENABLE

= HI

SC1, SC2, Data Load

±VS = ±12.0 V, VL = 5.0 V

–400

µA

Low Current, IIL

ENABLE = HI

SC1, SC2, Data Load

±VS = ±12.0 V, VL = 5.0 V

DIGITAL OUTPUTS

2.4

High Voltage, VOH

DB1–DB16; RIPPLE CLK, DIR

±VS = ±12.0 V, VL = 4.5 V

Low Voltage, VOL

IOH = 100 µA

0.4

DB1–DB16, RIPPLE CLK, DIR

±VS = ±12.0 V, VL = 5.5 V

IOL = 1.2 mA

THREE-STATE LEAKAGE

DB1–DB16 Only

Current IL

+VS = ±12.0 V, VL = 5.5 V

±100

µA

VOL = 0 V

+VS = ±12.0 V, VL = 5.5 V

±100

µA

VOH = 5.0 V

POWER SUPPLIES

Voltage Levels

+10.8

+13.2

+10.8

+13.2

+VS

–VS

–10.8

–13.2

–10.8

–13.2

+VL

+13.2

Current

±VS @ ±12 V

612

623

612

623

+IS

±VS @ ±13.2 V

619

630

619

630

+IL

±VL @ ±5.0 V

60.5

61.5

60.5

61.5

NOTES

1Refers to small signal bandwidth.

2Output offset dependent on value for R6.

3Refer to timing diagram.

4AD2S82A only.

5These pins are referenced to +VS (i.e., HI = +12 V, LO = 0 V).

Specifications subject to change without notice.

All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.

REV. B

–3–

AD2S81A/AD2S82A–SPECIFICATIONS (typical @ +258C unless otherwise noted)

AD2S81A

AD2S82A

Parameter

Conditions

Min

Typ

Max

Min

Typ

Max

Units

RATIO MULTIPLIER

177.6

AC Error Output Scaling

10 Bit

mV/Bit

12 Bit

44.4

mV/Bit

14 Bit

11.1

mV/Bit

16 Bit

2.775

mV/Bit

PHASE SENSITIVE DETECTOR

Output Offset Voltage

Gain

In Phase

w.r.t. REF

–0.882

–0.9

–0.918

–0.882

–0.9

–0.918

V rms/V dc

In Quadrature

w.r.t. REF

0.04

V rms/V dc

Input Bias Current

150

Input Impedance

±8

MΩ

Input Voltage

INTEGRATOR

Open-Loop Gain

At 10 kHz

Dead Zone Current (Hysteresis)

100

nA/LSB

Input Offset Voltage

Input Bias Current

±VS = ±10.8 V dc

±7

150

Output Voltage Range

VCO

±VS = ±12 V dc

1.0

1.1

1.0

1.1

MHz

Maximum Rate

VCO Rate

Positive DIR

7.1

7.9

8.7

7.1

7.9

8.7

kHz/µA

VCO Power Supply Sensitivity

Negative DIR

7.1

7.9

8.7

7.1

7.9

8.7

kHz/µA

Increase

+VS

+0.5

%/V

–VS

–8.0

%/V

Decrease

+VS

–8.0

%/V

Input Offset Voltage

–VS

+2.0

%/V

Input Bias Current

380

Input Bias Current Tempco

–1.22

±8

–1.22

±8

nA/°C

Input Voltage Range

Linearity of Absolute Rate

Full Range

% FSD

Over 0% to 50% of Full Range

% FSD

Reversion Error

±8

1.5

±8

1.5

% FSD

Sensitivity of Reversion Error

%/V of

to Symmetry of Power Supplies

±2.7

±3.0

±3.3

Asymmetry

VCO Output1, 2

V/LSB

POWER SUPPLIES

Voltage Levels

+10.8

+13.2

+10.8

+13.2

+VS

–VS

–10.8

–13.2

–10.8

–13.2

+VL

+13.2

Current

±VS @ ±12 V

612

623

612

623

+IS

±VS @ ±13.2 V

619

630

619

630

+IL

±VL @ ±5.0 V

60.5

61.5

60.5

61.5

NOTES

1The VCO output swings between ±3 V depending on the resolver direction.

ORDERING GUIDE

2AD2S82A only.

Operating

Specifications in boldface are tested on all production units at final electrical test.

Temperature

Package

Specifications subject to change without notice.

Accuracy

Ranges

Options*

AD2S81AJD

30 arc min

0°C to +70°C

D-28

AD2S82AHP

22 arc min

–40°C to +85°C

P-44A

AD2S82AJP

8 arc min

–40°C to +85°C

P-44A

AD2S82AKP

4 arc min

–40°C to +85°C

P-44A

AD2S82ALP

2 arc min

–40°C to +85°C

P-44A

*D = Ceramic DIP Package; P = Plastic Leaded Chip Carrier (PLCC) Package.

ESD SENSITIVITY

The AD2S81A and AD2S82A features an input protection circuit consisting of large “distributed” diodes and polysilicon series resistors to dissipate both high energy discharge (Human Body Model) and fast, low energy pulses (Charges Device Model).

The AD2S81A and AD2S82A is ESD protection Class II (2000 V min). Proper ESD precautions are strongly recommended to avoid functional damage or performance degradation. For further information on ESD precautions, refer to Analog Devices ESD Prevention Manual.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. B

Analog Devices AD2S82ALP, AD2S82AKP, AD2S82AJP, AD2S82AHP Datasheet

AD2S81A/AD2S82A

RECOMMENDED OPERATING CONDITIONS

Power Supply Voltage (+VS to –VS) . . . . . . . . . ±12 V dc ±10%

Power Supply Voltage VL . . . . . . . . . . . . . . . . . . +5 V dc ±10% Analog Input Voltage (SIN and COS) . . . . . . . . 2 V rms ±10%

Analog Input Voltage (REF) . . . . . . . . . . . . . . 1 V to 8 V peak Signal and Reference Harmonic Distortion . . . . . . . 10% (max) Phase Shift Between Signal and Reference . ±10 Degrees (max) Ambient Operating Temperature Range

Commercial (JD) . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Industrial (HP, JP, KP, LP) . . . . . . . . . . . . –40°C to +85°C

PIN FUNCTION DESCRIPTIONS

Mnemonic		Description

REFERENCE I/P		Reference Signal Input
DEMOD I/P		Demodulator Input
AC ERROR O/P		Ratio Multiplier Output
COS I/P		Cosine Input
ANALOG GND		Power Ground
SIGNAL GND		Resolver Signal Ground
SIN I/P		Sine Input
+VS		Positive Power Supply
DB1–DB16		Parallel Output Data
+VL		Logic Power Supply
ENABLE		Logic Hi-Output Data in High Impedance
		State Logic Lo Present Data to the Output Latches
BYTE SELECT		Logic Hi-Most Significant Byte to DB1–DB8
		Logic Lo-Most Significant Byte to DB1–DB8
INHIBIT		Logic Lo Inhibits Data Transfer to Output Latches
DIGITAL GND		Digital Ground
SC1–SC2*		Select Converter Resolution
DATA LOAD*		Logic Lo DB1–DB16 Inputs
		Logic Hi DB1–DB16 Outputs
BUSY		Converter Busy, Data Not Valid While Busy Hi
DIR		Logic State Defines Direction of Input Signal Rotation
RIPPLE CLK		Positive Pulse when Converter Output Changes from
		1s to All 0s or Vice Versa
–VS		Negative Power Supply
VCO I/P		VCO Input
INTEGRATOR I/P		Integrator Input
INTEGRATOR O/P		Integrator Output
DEMOD O/P		Demodulator Output
COMPLEMENT*		Active Logic Lo
VCO O/P*		VCO Output

*AD2S82A Only.
			Bit Weight Table
Binary	Resolution		Degrees	Minutes	Seconds
Bits (N)	(2N)		/Bit	/Bit	/Bit
0	1		360.0	21600.0	1296000.0
1	2		180.0	10800.0	648000.0
2	4		90.0	5400.0	324000.0
3	8		45.0	2700.0	162000.0
4	16		22.5	1350.0	81000.0

5	32		11.25	675.0	40500.0
6	64		5.625	337.5	20250.0
7	128		2.8125	168.75	10125.0
8	256		1.40625	84.375	5062.5
9	512		0.703125	42.1875	2531.25

10	1024		0.3515625	21.09375	1265.625
11	2048		0.1757813	10.546875	632.8125
12	4096		0.0878906	5.273438	316.40625
13	8192		0.0439453	2.636719	158.20313
14	16384		0.0219727	1.318359	79.10156

15	32768		0.0109836	0.659180	39.55078
16	65536		0.0054932	0.329590	19.77539
17	131072		0.0027466	0.164795	9.88770
18	262144		0.0013733	0.082397	4.94385

ABSOLUTE MAXIMUM RATINGS1 (with respect to GND)

+VS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . +14 V dc
–VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . –14 V dc
+VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . +VS
Reference . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . +14 V to –VS
SIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . +14 V to –VS
COS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . +14 V to –VS
Any Logical Input . . . . . . . . . . . . . . . . . . .	–0.4 V dc to +VL dc
Demodulator Input . . . . . . . . . . . . . . . . . .	. . . . . +14 V to –VS
Integrator Input . . . . . . . . . . . . . . . . . . . . .	. . . . . +14 V to –VS
VCO Input . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . +14 V to –VS
Power Dissipation . . . . . . . . . . . . . . . . . . .	. . . . . . . . . 860 mW
Operating Temperature	0°C to +70°C
Commercial (JD) . . . . . . . . . . . . . . . . . .	0°C to +70°C
Industrial (HP, JP, KP, LP) . . . . . . . . . .	. . . –40°C to +85°C
Storage Temperature (All Grades) . . . . . . .	. . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . .	. . . . . . . . . +300°C

CAUTION

1.Absolute Maximum Ratings are those values beyond which damage to the device may occur.

2.Correct polarity voltages must be maintained on the +VS and –VS pins.

AD2S81A/AD2S82A PIN CONFIGURATIONS

REFERENCE I/P

DEMOD O/P

DEMOD I/P

INTEGRATOR O/P

AC ERROR O/P

INTEGRATOR I/P

COS I/P

VCO I/P

ANALOG GND

–V

SIN I/P

RIPPLE CLK

AD2S81A

+VS

DIR

TOP VIEW

MSB DB1

(Not to Scale)

BUSY

DB2

DIGITAL GND

DB3

INHIBIT

DB4

BYTE SELECT

DB5

ENABLE

DB6

+VL

DB7

DB8 LSB

SIGNAL GND

ANALOG GND

COS I/P

AC ERROR O/P

DEMOD I/P

REFERENCE I/P

DEMOD O/P

INTEGRATOR O/P

INTEGRATOR I/P

VCO O/P

VCO I/P

SIN O/P

PIN 1

–V

IDENTIFIER

+VS

RIPPLE CLK

DIR

MSB DB1 10

BUSY

DB2 11

AD2S82A

DATA LOAD

DB3 12

TOP VIEW

COMPLEMENT

DB4 13

SC2

(Not to Scale)

DB5 14

SC1

DB6 15

DIGITAL GND

DB7 16

INHIBIT

DB8 17

DB9

DB10

DB11

DB12

DB13

DB14

DB15

DB16LSB

ENABLE

BYTE SELECT

NC = NO CONNECT

REV. B

–5–

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