ANALOG DEVICES AD5307, AD5317, AD5327 Service Manual

2.5 V to 5.5 V, 400 μA, Quad Voltage Output, 8-/10-/12-Bit DACs in 16-Lead TSSOP

FEATURES

AD5307: 4 buffered 8-bit DACs in 16-lead TSSOP A version: ±1 LSB INL; B version: ±0.625 LSB INL

AD5317: 4 buffered 10-bit DACs in 16-lead TSSOP A version: ±4 LSB INL; B version: ±2.5 LSB INL AD5327: 4 buffered 12-bit DACs in 16-lead TSSOP A version: ±16 LSB INL; B version: ±10 LSB INL Low power operation: 400 μA @ 3 V, 500 μA @ 5 V

2.5 V to 5.5 V power supply

Guaranteed monotonic by design over all codes

Power down to 90 nA @ 3 V, 300 nA @ 5 V (LDAC pin) Double-buffered input logic

Buffered/unbuffered reference input options Output range: 0 V to VREF or 0 V to 2 VREF Power-on reset to 0 V

Simultaneous update of outputs (LDAC pin) Asynchronous clear facility (CLR pin)

Low power, SPI®-, QSPI™-, MICROWIRE™-, and DSPcompatible 3-wire serial interface

SDO daisy-chaining option

On-chip rail-to-rail output buffer amplifiers Temperature range of −40°C to +105°C

APPLICATIONS

Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators

Industrial process control

AD5307/AD5317/AD5327

GENERAL DESCRIPTION

The AD5307/AD5317/AD53271 are quad 8-,10-,12-bit buffered voltage-output DACs in 16-lead TSSOP that operate from single 2.5 V to 5.5 V supplies and consume 400 μA at 3 V. Their onchip output amplifiers allow the outputs to swing rail-to-rail with a slew rate of 0.7 V/μs. The AD5307/AD5317/AD5327 utilize versatile 3-wire serial interfaces that operate at clock rates up to 30 MHz; these parts are compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards.

The references for the four DACs are derived from two reference pins (one per DAC pair). These reference inputs can be configured as buffered or unbuffered inputs. Each part incorporates a poweron reset circuit, ensuring that the DAC outputs power up to 0 V and remain there until a valid write to the device takes place.

There is also an asynchronous active low CLR pin that clears all DACs to 0 V. The outputs of all DACs can be updated simultaneously using the asynchronous LDAC input. Each part contains a power-down feature that reduces the current consumption of the device to 300 nA @ 5 V (90 nA @ 3 V). The parts can also be used in daisy-chaining applications using the SDO pin.

All three parts are offered in the same pinout, allowing users to select the amount of resolution appropriate for their application without redesigning their circuit board.

FUNCTIONAL BLOCK DIAGRAM

	VDD		VREFAB
AD5307/AD5317/AD5327				GAIN-SELECT
	LDAC				LOGIC
	INPUT	DAC	STRING	BUFFER		VOUTA
	REGISTER	REGISTER	DAC A
SCLK	INPUT	DAC	STRING	BUFFER		VOUTB
	REGISTER	REGISTER	DAC B
SYNC	INTERFACE
	LOGIC
	INPUT	DAC	STRING	BUFFER		VOUTC
	REGISTER	REGISTER	DAC C
DIN
	INPUT	DAC	STRING	BUFFER		VOUTD
	REGISTER	REGISTER	DAC D
SDO	POWER-ON
				POWER-DOWN
	RESET
				LOGIC		02067-001
DCEN	LDAC CLR		VREFCD	PD	GND

Figure 1.

1 Protected by U.S. Patent No. 5,969,657; other patents pending.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: [phone]	www.analog.com
Fax: [phone]	©2006 Analog Devices, Inc. All rights reserved.

AD5307/AD5317/AD5327

TABLE OF CONTENTS
Features ..............................................................................................	1
Applications.......................................................................................	1
General Description .........................................................................	1
Functional Block Diagram ..............................................................	1
Revision History ...............................................................................	2
Specifications.....................................................................................	3
AC Characteristics........................................................................	5
Timing Characteristics ................................................................	5
Absolute Maximum Ratings............................................................	7
ESD Caution..................................................................................	7
Pin Configuration and Function Descriptions.............................	8
Typical Performance Characteristics .............................................	9
Terminology ....................................................................................	13
Transfer Function ...........................................................................	14
Functional Description ..................................................................	15
Digital-to-Analog Section .........................................................	15
Resistor String.............................................................................	15
DAC Reference Inputs ...............................................................	15
Output Amplifier........................................................................	16
Power-On Reset ..........................................................................	16
Serial Interface ................................................................................	17
REVISION HISTORY
3/06—Rev. B to Rev. C
Changes to Table 3............................................................................	5
Changes to Ordering Guide ..........................................................	25
10/05—Rev. A to Rev. B
Updated Format..................................................................	Universal
Changes to Bipolar Operation Section ........................................	21
Changes to Ordering Guide ..........................................................	25

Input Shift Register ....................................................................	17
Control Bits .................................................................................	17
Low Power Serial Interface .......................................................	18
Daisy Chaining ...........................................................................	18
Double-Buffered Interface ........................................................	18
Load DAC Input (LDAC)..........................................................	18
Power-Down Mode....................................................................	18
Microprocessor Interfacing.......................................................	19
Applications.....................................................................................	20
Typical Application Circuit.......................................................	20
Driving VDD from the Reference Voltage ................................	20
Bipolar Operation.......................................................................	20
Opto-Isolated Interface for Process-Control Applications...	21
Decoding Multiple AD5307/AD5317/AD5327 Devices.......	21
AD5307/AD5317/AD5327 as Digitally Programmable
Window Detectors .....................................................................	21
Daisy Chaining ...........................................................................	22
Power Supply Bypassing and Grounding................................	22
Outline Dimensions .......................................................................	24
Ordering Guide ..........................................................................	25

8/03—Rev. 0 to Rev. A
Added A Version ................................................................	Universal
Changes to Features ..........................................................................	1
Changes to Specifications.................................................................	2
Changes to Absolute Maximum Ratings........................................	6
Changes to Ordering Guide .............................................................	6
Changes to TPC 21.........................................................................	12
Added Octals section to Table II ..................................................	20
Updated Outline Dimensions.......................................................	21

Rev. C | Page 2 of 28

AD5307/AD5317/AD5327

SPECIFICATIONS

VDD = 2.5 V to 5.5 V, VREF = 2 V, RL = 2 kΩ to GND, CL = 200 pF to GND. All specifications TMIN to TMAX, unless otherwise noted.

Table 1.

		A Version1			B Version
Parameter2	Min	Typ	Max	Min	Typ	Max	Unit	Conditions/Comments
DC PERFORMANCE3, 4
AD5307
Resolution		8			8		Bits
Relative Accuracy		±0.15	±1		±0.15	±0.625	LSB
Differential Nonlinearity		±0.02	±0.25		±0.02	±0.25	LSB	Guaranteed monotonic by design
								over all codes
AD5317
Resolution		10			10		Bits
Relative Accuracy		±0.5	±4		±0.5	±2.5	LSB
Differential Nonlinearity		±0.05	±0.5		±0.05	±0.5	LSB	Guaranteed monotonic by design
								over all codes
AD5327
Resolution		12			12		Bits
Relative Accuracy		±2	±16		±2	±10	LSB
Differential Nonlinearity		±0.2	±1		±0.2	±1	LSB	Guaranteed monotonic by design
								over all codes
Offset Error		±5	±60		±5	±60	mV	VDD = 4.5 V, gain = 2; see Figure 29
								and Figure 30
Gain Error		±0.3	±1.25		±0.3	±1.25	% FSR	VDD = 4.5 V, gain = 2; see Figure 29
								and Figure 30
Lower Dead Band5		10	60		10	60	mV	See Figure 29, lower dead band
								exists only if offset error is negative
Upper Dead Band		10	60		10	60	mV	See Figure 30, upper dead band
								exists only if VREF = VDD and offset
								plus gain error is positive
Offset Error Drift6		−12			−12		ppm of
							FSR/°C
Gain Error Drift		−5			−5		ppm of
							FSR/°C
DC Power Supply Rejection Ratio		−60			−60		dB	∆VDD = ±10%
DC Crosstalk		200			200		mV	RL = 2 kΩ to GND or VDD
DAC REFERENCE INPUTS
VREF Input Range	1		VDD	1		VDD	V	Buffered reference mode
	0.25		VDD	0.25		VDD	V	Unbuffered reference mode
VREF Input Impedance (RDAC)		>10			>10		MΩ	Buffered reference mode and
								power-down mode
	74	90		74	90		kΩ	Unbuffered reference mode,
								0 V to VREF output range
	37	45		37	45		kΩ	Unbuffered reference mode,
								0 V to 2 VREF output range
Reference Feedthrough		−90			−90		dB	Frequency = 10 kHz
Channel-to-Channel Isolation		−75			−75		dB	Frequency = 10 kHz
OUTPUT CHARACTERISTICS
Minimum Output Voltage7		0.001			0.001		V	A measure of the minimum drive
								capability of the output amplifier
Maximum Output Voltage		VDD −			VDD −		V	A measure of the maximum drive
		0.001			0.001			capability of the output amplifier
DC Output Impedance		0.5			0.5		Ω
Short-Circuit Current		25			25		mA	VDD = 5 V
		16			16		mA	VDD = 3 V
Power-Up Time		2.5			2.5		μs	Coming out of power-down mode,
								VDD = 5 V
		5			5		μs	Coming out of power-down mode,
								VDD = 3 V

Rev. C | Page 3 of 28

AD5307/AD5317/AD5327

		A Version1			B Version
Parameter2	Min	Typ	Max	Min	Typ	Max	Unit	Conditions/Comments
LOGIC INPUTS
Input Current			±1			±1	mA
Input Low Voltage, VIL			0.8			0.8	V	VDD = 5 V ± 10%
			0.6			0.6	V	VDD = 3 V ± 10%
			0.5			0.5	V	VDD = 2.5 V
Input High Voltage, VIH	1.7			1.7			V	VDD = 2.5 V to 5.5 V; TTL and
(Excluding DCEN)								1.8 V CMOS compatible
Input High Voltage, VIH	2.4			2.4				VDD = 5 V ± 10%
(DCEN)
	2.1			2.1			V	VDD = 3 V ± 10%
	2.0			2.0			V	VDD = 2.5 V
Pin Capacitance		3			3		pF
LOGIC OUTPUT (SDO)
VDD = 4.5 V to 5.5 V
Output Low Voltage, VOL		0.4				0.4	V	ISINK = 2 mA
Output High Voltage, VOH	VDD − 1			VDD − 1			V	ISOURCE = 2 mA
VDD = 2.5 V to 3.6 V
Output Low Voltage, VOL		0.4		0.4			V	ISINK = 2 mA
Output High Voltage, VOH	VDD −			VDD −			V	ISOURCE = 2 mA
	0.5			0.5
Floating State Leakage Current			±1			±1	μA	DCEN = GND
Floating State Output Capacitance		3			3		pF	DCEN = GND
POWER REQUIREMENTS
VDD	2.5		5.5	2.5		5.5	V
IDD (Normal Mode)8								VIH = VDD and VIL = GND
VDD = 4.5 V to 5.5 V		500	900		500	900	μA	All DACs in unbuffered mode; in
VDD = 2.5 V to 3.6 V		400	750		400	750	μA	buffered mode, extra current is
								typically x mA per DAC, where
								x = 5 mA + VREF/RDAC
IDD (Power-Down Mode)								VIH = VDD and VIL = GND
VDD = 4.5 V to 5.5 V		0.3	1		0.3	1	μA
VDD = 2.5 V to 3.6 V		0.09	1		0.09	1	μA

1 Temperature range (A, B versions): −40°C to +105°C; typical at +25°C. 2 See the Terminology section.

3 DC specifications tested with the outputs unloaded, unless otherwise noted.

4 Linearity is tested using a reduced code range: AD5307 (Code 8 to Code 255); AD5317 (Code 28 to Code 1023); AD5327 (Code 115 to Code 4095). 5 This corresponds to x codes, where x = deadband voltage/LSB size.

6 Guaranteed by design and characterization; not production tested.

7 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and offset plus gain error must be positive.

8 Interface inactive. All DACs active. DAC outputs unloaded.

Rev. C | Page 4 of 28

AD5307/AD5317/AD5327

AC CHARACTERISTICS

VDD = 2.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND. All specifications TMIN to TMAX, unless otherwise noted.

Table 2.

		A, B Versions1
Parameter2, 3	Min	Typ	Max	Unit	Conditions/Comments
Output Voltage Settling Time					VREF = VDD = 5 V
AD5307		6	8	μs	1/4 scale to 3/4 scale change (0x40 to 0xC0)
AD5317		7	9	μs	1/4 scale to 3/4 scale change (0x100 to 0x300)
AD5327		8	10	μs	1/4 scale to 3/4 scale change (0x400 to 0xC00)
Slew Rate		0.7		V/μs
Major-Code Change Glitch Energy		12		nV-s	1 LSB change around major carry
Digital Feedthrough		0.5		nV-s
SDO Feedthrough		4		nV-s	Daisy-chain mode; SDO load is 10 pF
Digital Crosstalk		0.5		nV-s
Analog Crosstalk		1		nV-s
DAC-to-DAC Crosstalk		3		nV-s
Multiplying Bandwidth		200		kHz	VREF = 2 V ± 0.1 V p-p; unbuffered mode
Total Harmonic Distortion		−70		dB	VREF = 2.5 V ± 0.1 V p-p; frequency = 10 kHz

1 Temperature range (A, B versions): −40°C to +105°C; typical at +25°C. 2 Guaranteed by design and characterization; not production tested. 3 See the Terminology section.

TIMING CHARACTERISTICS

VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.

Table 3.

A, B Versions

Parameter1, 2,

Limit at TMIN, TMAX

Unit

Conditions/Comments

3

t1

33

ns min

SCLK cycle time

t2

13

ns min

SCLK high time

t3

13

ns min

SCLK low time

t4

13

ns min

to SCLK falling edge set-up time

SYNC

t5

5

ns min

Data set-up time

t6

4.5

ns min

Data hold time

t7

5

ns min

rising edge

SCLK falling edge to

SYNC

t8

50

ns min

Minimum

SYNC

high time

t9

20

ns min

LDAC

pulse width

t10

20

ns min

SCLK falling edge to

LDAC

rising edge

t11

20

ns min

CLR

pulse width

t12

0

ns min

SCLK falling edge to

LDAC

falling edge

t134, 5

20

ns max

SCLK rising edge to SDO valid (VDD = 3.6 V to 5.5 V)

25

ns max

SCLK rising edge to SDO valid (VDD = 2.5 V to 3.5 V)

t14

5

ns min

SCLK falling edge to

SYNC

rising edge

t15

8

ns min

SYNC

rising edge to SCLK rising edge

t16

0

ns min

falling edge

SYNC

rising edge to

LDAC

1 Guaranteed by design and characterization; not production tested.

2 All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 See Figure 3 and Figure 4.

4 This is measured with the load circuit of Figure 2. t13 determines maximum SCLK frequency in daisy-chain mode. 5 Daisy-chain mode only.

Rev. C | Page 5 of 28

AD5307/AD5317/AD5327

2mA IOL

TO OUTPUT

PIN CL 50pF

VOH (MIN)

2mA IOH	02067-002

Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications

		t1
SCLK
t4	t3	t2	t7
t8
SYNC
	t6
	t5

DIN

DB15

DB0

t9

t12

LDAC1

t10

LDAC2

t11

CLR

NOTES

1ASYNCHRONOUS LDAC UPDATE MODE.

2SYNCHRONOUS LDAC UPDATE MODE.

02067-003

Figure 3. Serial Interface Timing Diagram

		t1
SCLK
t8	t4	t2	t14
		t3
SYNC				t15
			t16
				t9

LDAC	t6
	t5
DIN	DB15	DB0 DB15'	DB0'
	INPUT WORD FOR DAC N	t13	INPUT WORD FOR DAC (N+1)
SDO		DB15	DB0
	UNDEFINED		INPUT WORD FOR DAC N

02067-004

Figure 4. Daisy-Chaining Timing Diagram

Rev. C | Page 6 of 28

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter1	Ratings
VDD to GND	−0.3 V to +7 V
Digital Input Voltage to GND	−0.3 V to VDD + 0.3 V
Digital Output Voltage to GND	−0.3 V to VDD + 0.3 V
Reference Input Voltage to GND	−0.3 V to VDD + 0.3 V
VOUTA − VOUTD to GND	−0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (A, B Versions)	−40°C to +105°C
Storage Temperature Range	−65°C to +150°C
Junction Temperature (TJ max)	150°C
16-Lead TSSOP
Power Dissipation	(TJ max − TA)/θJA
θJA Thermal Impedance	150.4°C/W
Reflow Soldering
Peak Temperature	220°C
Time at Peak Temperature	10 sec to 40 sec

1 Transient currents of up to 100 mA do not cause SCR latch-up.

AD5307/AD5317/AD5327

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. C | Page 7 of 28

AD5307/AD5317/AD5327

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

		CLR		1		16	SDO
				2	AD5307/	15		SYNC
	LDAC
	VDD			3	AD5317/	14	SCLK
V A				4	AD5327	13	DIN
	OUT				TOP VIEW
VOUTB				5			GND
					(Not to Scale) 12
VOUTC				6		11	VOUTD
VREFAB				7		10
							PD
VREFCD				8		9	DCEN

Figure 5. Pin Configuration

02067-005

Table 5. Pin Function Descriptions

Pin
No.		Mnemonic					Description
1							Active Low Control Input. Loads all 0s to all input and DAC registers. Therefore, the outputs also go to 0 V.
		CLR
2							Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. Pulsing this
		LDAC
							pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous
							update of all DAC outputs. Alternatively, this pin can be tied permanently low.
3		VDD					Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 μF
							capacitor in parallel with a 0.1 μF capacitor to GND.
4		VOUTA					Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
5		VOUTB					Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
6		VOUTC					Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
7		VREFAB					Reference Input Pin for DAC A and DAC B. It can be configured as a buffered or unbuffered input to each or both of
							the DACs, depending on the state of the BUF bits in the serial input words to DAC A and DAC B. It has an input range
							of 0.25 V to VDD in unbuffered mode and 1 V to VDD in buffered mode.
8		VREFCD					Reference Input Pin for DAC C and DAC D. It can be configured as a buffered or unbuffered input to each or both of
							the DACs, depending on the state of the BUF bits in the serial input words to DAC C and DAC D. It has an input range
							of 0.25 V to VDD in unbuffered mode and 1 V to VDD in buffered mode.
9		DCEN					Enables the Daisy-Chaining Option. It should be tied high if the part is being used in a daisy chain, and tied low if it is
							being used in standalone mode.
10							Active Low Control Input. It acts like a hardware power-down option. All DACs go into power-down mode when this
		PD
							pin is tied low. The DAC outputs go into a high impedance state, and the current consumption of the part drops to
							300 nA @ 5 V (90 nA @ 3 V).
11		VOUTD					Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
12		GND					Ground Reference Point for All Circuitry on the Part.
13		DIN					Serial Data Input. These devices each have a 16-bit shift register. Data is clocked into the register on the falling edge of
							the serial clock input. The DIN input buffer is powered down after each write cycle.
14		SCLK					Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be
							transferred at rates of up to 30 MHz. The SCLK input buffer is powered down after each write cycle.
15							Active Low Control Input. This is the frame synchronization signal for the input data. When				goes low, it powers
		SYNC							SYNC
							on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the
							following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of	SYNC		acts as an interrupt and
							the write sequence is ignored by the device.
16	SDO						Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the data in
							the shift register for diagnostic purposes. The serial data is transferred on the rising edge of SCLK and is valid on the
							falling edge of the clock.

Rev. C | Page 8 of 28

TYPICAL PERFORMANCE CHARACTERISTICS

	1.0
		TA = 25°C
		VDD = 5V
	0.5
(LSB)
INL ERROR	0
	–0.5
	–1.0					02067-006
		50	100	150	200	250
	0
				CODE

Figure 6. AD5307 INL

	3
		TA = 25°C
	2	VDD = 5V
(LSB)	1
INL ERROR	0
	–1
	–2					02067-007
	–3
		200	400	600	900	1000
	0
				CODE

Figure 7. AD5317 INL

	12	TA = 25°C
		VDD = 5V
	8
(LSB)	4
INL ERROR	0
	–4
	–8				02067-008
	–12
		1000	2000	3000	4000
	0
			CODE

Figure 8. AD5327 INL

			AD5307/AD5317/AD5327
	0.3	TA = 25°C
	0.2	VDD = 5V
(LSB)	0.1
DNL ERROR	0
	–0.1
	–0.2					02067-009
	–0.3
		50	100	150	200	250
	0
				CODE

Figure 9. AD5307 DNL

	0.6
		TA = 25°C
	0.4	VDD = 5V
(LSB)	0.2
ERRORDNL	–0.2
	0
	–0.4					02067-010
	–0.6
		200	400	600	800	1000
	0

CODE

Figure 10. AD5317 DNL

	1.0
			TA =		25°C
			VDD = 5V
(LSB)	0.5
ERRORDNL	0
	–0.5																02067-011
	–1.0
			1000										2000	3000		4000
	0

CODE

Figure 11. AD5327 DNL

Rev. C | Page 9 of 28