Analog Devices AD5232BRU50-REEL7, AD5232BRU50, AD5232BRU100-REEL7, AD5232BRU100, AD5232BRU10-REEL7 Datasheet

a

8-Bit Dual Nonvolatile Memory

Digital Potentiometer

FEATURES

Nonvolatile Memory Preset Maintains Wiper Settings Dual Channel, 256-Position Resolution

Full Monotonic Operation DNL < 1 LSB

10 k , 50 k , 100 k Terminal Resistance

Linear or Log Taper Settings

Push-Button Increment/Decrement Compatible SPI-Compatible Serial Data Input with Readback

Function

3 V to 5 V Single Supply or 2.5 V Dual Supply

Operation

14 Bytes of User EEMEM Nonvolatile Memory for Constant Storage

Permanent Memory Write Protection 100-Year Typical Data Retention TA = 55 C

APPLICATIONS

Mechanical Potentiometer Replacement

Instrumentation: Gain, Offset Adjustment

Programmable Voltage-to-Current Conversion

Programmable Filters, Delays, Time Constants

Line Impedance Matching

Power Supply Adjustment

DIP Switch Setting

GENERAL DESCRIPTION

The AD5232 device provides a nonvolatile, dual-channel, digitally controlled variable resistor (VR) with 256-position resolution. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. The AD5232’s versatile programming via a microcontroller allows multiple modes of operation and adjustment.

In the direct program mode a predetermined setting of the RDAC register can be loaded directly from the microcontroller. Another key mode of operation allows the RDAC register to be refreshed with the setting previously stored in the EEMEM register. When changes are made to the RDAC register to establish a new wiper position, the value of the setting can be saved into the EEMEM by executing an EEMEM save operation. Once the settings are saved in the EEMEM register these values will be automatically transferred to the RDAC register to set the wiper position at system power ON. Such operation is enabled by the internal preset strobe and the preset can also be accessed externally.

All internal register contents can be read out of the serial data output (SDO). This includes the RDAC1 and RDAC2 registers, the corresponding nonvolatile EEMEM1 and EEMEM2 registers, and the 14 spare USER EEMEM registers available for constant storage.

*Patent pending.

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AD5232*

FUNCTIONAL BLOCK DIAGRAM

CS			AD5232
		RDAC1	VDD
CLK	ADDR		RDAC1
	DECODE	REGISTER
			A1
SDI	SDI
			W1
GND	SERIAL	EEMEM1	B1
	INTERFACE
SDO	SDO	RDAC2	RDAC2
		REGISTER	A2
WP	EEMEM		W2
RDY	CONTROL		B2
		EEMEM2
PR	14 BYTES
			VSS
	USER EEMEM

The basic mode of adjustment is the increment and decrement command controlling the present setting of the Wiper position setting (RDAC) register. An internal scratch pad RDAC register can be moved UP or DOWN one step of the nominal terminal resistance between terminals A and B. This linearly changes the wiper to B terminal resistance (RWB) by one position segment of the devices’ end-to-end resistance (RAB). For exponential/logarithmic changes in wiper setting, a left/right shift command adjusts levels in ± 6 dB steps, which can be useful for audio and light alarm applications.

The AD5232 is available in a thin TSSOP-16 package. All parts are guaranteed to operate over the extended industrial temperature range of –40° C to +85° C. An evaluation board is available, Part Number: AD5232EVAL.

AB	100
R	75
OFPERCENTNOMINAL RESISTANCEEND-TO-END – %
	50
	25
			RWB					RWA
	0
			64	128		192		256
	0

CODE – Decimal

Figure 1. Symmetrical RDAC Operation

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Tel: [phone]	www.analog.com
Fax: [phone]	© Analog Devices, Inc., 2001

AD5232–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS, 10 k , 50 k , 100 k VERSIONS

( VDD = 3 V 10% or 5 V 10% and VSS = 0 V, VA = +VDD, VB = 0 V, –40 C < TA < +85 C unless otherwise noted.)

Parameter	Symbol		Conditions	Min	Typ1	Max	Unit
DC CHARACTERISTICS
RHEOSTAT MODE – Specifications Apply to All VRs					± 1/2
Resistor Differential Nonlinearity2	R-DNL		RWB, VA = NC	–1		+1	LSB
Resistor Nonlinearity2	R-INL		RWB, VA = NC	–0.4		+0.4	% FS
Nominal Resistor Tolerance	RAB			–40		+20	%
Resistance Temperature Coefficient	RAB/ T				600		ppm/° C
Wiper Resistance	RW		IW = 100 µ A, VDD = 5.5 V, Code = 1EH		5	100	Ω
	RW		IW = 100 µ A, VDD = 3 V, Code = 1EH		200		Ω
POTENTIOMETER DIVIDER MODE — Specifications Apply to All VRs
Resolution	N			8	± 1/2		Bits
Differential Nonlinearity3	DNL			–1		+1	LSB
Integral Nonlinearity3	INL			–0.4		+0.4	% FS
Voltage Divider Temperature Coefficient	VW/ T		Code = Half-Scale		15		ppm/° C
Full-Scale Error	VWFSE		Code = Full-Scale	–3		0	% FS
Zero-Scale Error	VWZSE		Code = Zero-Scale	0		+3	% FS
RESISTOR TERMINALS
Terminal Voltage Range4	VA,B,W			VSS		VDD	V
Capacitance5 Ax, Bx	CA,B		f = 1 MHz, Measured to GND,
Capacitance5 Wx			Code = Half-Scale		45		pF
	CW		f = 1 MHz, Measured to GND,
			Code = Half-Scale		60		pF
Common-Mode Leakage Current5, 6	ICM		VW = VDD/2		0.01	1	µ A
DIGITAL INPUTS AND OUTPUTS
Input Logic High	VIH		With Respect to GND, VDD = 5 V	2.4			V
Input Logic Low	VIL		With Respect to GND, VDD = 5 V			0.8	V
Input Logic High	VIH		With Respect to GND, VDD= 3 V	2.1			V
Input Logic Low	VIL		With Respect to GND, VDD = 3 V			0.6	V
Input Logic High	VIH		With Respect to GND, VDD = +2.5 V,	2.0			V
Input Logic Low	VIL		VSS = –2.5 V
			With Respect to GND, VDD = +2.5 V,		0.5		V
			VSS = –2.5 V
Output Logic High (SDO and RDY)	VOH		RPULL-UP = 2.2 kΩ to 5 V	4.9			V
Output Logic Low	VOL		IOL = 1.6 mA, VLOGIC = 5 V			0.4	V
Input Current	IIL		VIN = 0 V or VDD			± 2.5	µ A
Input Capacitance5	CIL				4		pF
POWER SUPPLIES
Single-Supply Power Range	VDD		VSS = 0 V	2.7		5.5	V
Dual-Supply Power Range	VDD/VSS			± 2.25		± 2.75	V
Positive Supply Current	IDD		VIH = VDD or VIL = GND		3.5	10	µ A
Programming Mode Current	IDD(PG)		VIH = VDD or VIL = GND		35		mA
Read Mode Current7	IDD(XFR)		VIH = VDD or VIL = GND	0.9	3	9	mA
Negative Supply Current	ISS		VIH = VDD or VIL = GND,				µ A
Power Dissipation8			VDD = +2.5 V, VSS = –2.5 V		3.5	10
	PDISS		VIH = VDD or VIL = GND		0.018	0.05	mW
Power Supply Sensitivity5	PSS		VDD = 5 V ± 10%		0.002	0.01	%/%

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AD5232

Parameter	Symbol	Conditions		Min Typ1	Max	Unit
DYNAMIC CHARACTERISTICS5, 9		–3 dB, BW_10 kΩ , R = 10 kΩ
Bandwidth				500		kHz
Total Harmonic Distortion	THDW	VA = 1 V rms, VB = 0 V, f = 1 kHz,
	THDW	RAB = 10 kΩ		0.022		%
		VA =1 V rms, VB = 0 V, f = 1 kHz,
		RAB = 50 kΩ , 100 kΩ		0.045		%
VW Settling Time	tS	VDD = 5 V, VSS = 0 V, VA = VDD, VB = 0 V,
		VW = 0.50% Error Band, Code 00H to 80H
		For RAB = 10 kΩ /50 kΩ	/100 kΩ	0.65/3/6		µ s
Resistor Noise Voltage	eN_WB	RWB = 5 kΩ , f = 1 kHz		9		nV/√ Hz
		Crosstalk (CW1/CW2)	CT
		VA = VDD, VB = 0 V, Measure VW with
		Adjacent VR Making Full-Scale Code Change		–5		nV-s
Analog Crosstalk (CW1/CW2)	CTA	VA1 = VDD, VB1 = 0 V, Measure VW1
		with VW2 = 5 V p-p @ f = 10 kHz,
		Code1 = 80H; Code2 = FFH		–70		dB
INTERFACE TIMING CHARACTERISTICS – Applies to All Parts5, 10
Clock Cycle Time (tCYC)	t1			20		ns
CS Setup Time	t2			10		ns
CLK Shutdown Time to CS Rise	t3			1		tCYC
Input Clock Pulsewidth	t 4 , t 5	Clock Level High or Low		10		ns
Data Setup Time	t6	From Positive CLK Transition		5		ns
Data Hold Time	t7	From Positive CLK Transition		5		ns
CS to SDO-SPI Line Acquire	t8				40	ns
CS to SDO-SPI Line Release	t 9	RP = 2.2 kΩ , CL < 20 pF			50	ns
CLK to SDO Propagation Delay11	t10				50	ns
CLK to SDO Data Hold Time	t11	RP = 2.2 kΩ , CL < 20 pF		0		ns
CS High Pulsewidth12	t12			10		ns
CS High to CS High12	t 13			4		tCYC
RDY Rise to CS Fall	t 14			0		ns
CS Rise to RDY Fall Time	t 15			0.1	0.15	ms
Read/Store to Nonvolatile EEMEM13	t 16	Applies to Command 2H, 3H, 9H			25	ms
CS Rise to Clock Rise/Fall Setup	t17			10		ns
Preset Pulsewidth (Asynchronous)	tPRW	Not Shown in Timing Diagram		50		ns
Preset Response Time to RDY High	tPRESP	PR Pulsed Low to Refreshed				µ s
		Wiper Positions		70
FLASH/EE MEMORY RELIABILITY CHARACTERISTICS
Endurance14				100		K Cycles
Data Retention15				100		Years

NOTES

1Typical parameters represent average readings at 25° C and VDD = 5 V.

2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper postions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W ~ 50 µ A @ VDD = 2.7 V and

IW ~ 400 µ A @ VDD = 5 V for the RAB = 10 kΩ version, IW ~ 50 µ A for the RAB = 50 kΩ and IW ~ 25 µ A for the RAB = 100 kΩ version. See Figure 13.

3INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = VSS. DNL specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 14.

4Resistor terminals A, B, W have no limitations on polarity with respect to each other. Dual Supply Operation enables ground-referenced bipolar signal adjustment. 5Guaranteed by design and not subject to production test.

6Common-mode leakage current is a measure of the dc leakage from any terminal A, B, W to a common-mode bias level of VDD/2.

7Transfer (XFR) Mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 9.

8PDISS is calculated from (IDD VDD) + (ISS VSS).

9All dynamic characteristics use VDD = +2.5 V and VSS = –2.5 V unless otherwise noted.

10See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V or 5 V.

11Propagation delay depends on value of VDD, RPULL_UP, and CL. See applications text. 12Valid for commands that do not activate the RDY pin.

13RDY pin low only for instruction commands 8, 9, 10, 2, 3, and the PR hardware pulse: CMD_8 ~ 1 ms; CMD_9,10 ~ 0.12 ms; CMD_2,3 ~ 20 ms. Device operation at TA = –40° C and VDD < 3 V extends the save time to 35 ms.

14Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at V DD = 2.7 V, TA = –40° C to +85° C, typical endurance at 25° C is 700,000 cycles.

15Retention lifetime equivalent at junction temperature (TJ) = 55° C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV will derate with junction temperature as shown in Figure 23 in the Flash/EE Memory description section of this data sheet. The AD5232 contains 9,646 transistors. Die size: 69 mil 115 mil, 7,993 sq. mil.

Specifications subject to change without notice

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AD5232

			CPHA = 1
CS
				t12
		t1	t3	t13
	t2
CLK		t5
CPOL = 1				t17
		t4
	t8		t10	t9
			t11
SDO	*	MSB	LSB OUT
			t7
			t6
SDI		MSB	LSB
	t14			t15
RDY				t16

*NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED.

THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.

Figure 2a. CPHA = 1 Timing Diagram

CS		CPHA = 0
				t12
		t1	t3	t13
	t2	t5		t17
CLK		t4
CPOL = 0
	t8	t10	t11
				t9
SDO	MSB OUT	LSB		*
		t7
		t6
SDI	MSB IN	LSB
	t14			t15
				t16
RDY

*NOT DEFINED, BUT NORMALLY MSB OF CHARACTER JUST RECEIVED.

THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.

Figure 2b. CPHA = 0 Timing Diagram

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AD5232

ABSOLUTE MAXIMUM RATINGS1

(TA = 25° C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . .	. . . . .	. . . . . –0.3 V, +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . .	. . . .	. . . . +0.3 V, –7 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . .	. . . .	. . . . . . . . . . . . 7 V
VA, VB, VW to GND . . . . . . . . . . . . .	VSS – 0.3 V, VDD + 0.3 V
AX – BX, AX – WX, BX – WX		± 20 mA
Intermittent2 . . . . . . . . . . . . . . . . .	. . . .
Continuous . . . . . . . . . . . . . . . . . .	. . . .	. . . . . . . . . ± 2 mA
Digital Inputs and Output Voltage to		–0.3 V, VDD +0.3 V
GND . . . . . . . . . . . . . . . . . . . . . . .	. . .
Operating Temperature Range3 . . . . .	. . . .	. . –40° C to +85° C
Maximum Junction Temperature (TJ	Max)	. . . . . . . . 150° C
Storage Temperature . . . . . . . . . . . . .	. . . .	. –65° C to +150° C
Lead Temperature, Soldering		215° C
Vapor Phase (60 sec) . . . . . . . . . . .	. . . .
Infrared (15 sec) . . . . . . . . . . . . . .	. . . .	. . . . . . . . . 220° C

Package Power Dissipation . . . . . . . . . . . . .	(TJ Max – TA)/ JA
Thermal Resistance Junction-to-Ambient JA,	150° C/W
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance Junction-to-Case JC,	28° C/W
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . .

NOTES

1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance.

3Includes programming of nonvolatile memory.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5232 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

WARNING!

ESD SENSITIVE DEVICE

						Number of
	Number of	End-to-End	Temperature	Package	Package	Devices per	Branding*
Model	Channels	R AB (k )	Range (° C)	Description	Option	Container	Information
AD5232BRU10	2	10	–40 to +85	TSSOP-16	RU-16	96	5232B10
AD5232BRU10-REEL7	2	10	–40 to +85	TSSOP-16	RU-16	1,000	5232B10
AD5232BRU50	2	50	–40 to +85	TSSOP-16	RU-16	96	5232B50
AD5232BRU50-REEL7	2	50	–40 to +85	TSSOP-16	RU-16	1,000	5232B50
AD5232BRU100	2	100	–40 to +85	TSSOP-16	RU-16	96	5232BC
AD5232BRU100-REEL7	2	100	–40 to +85	TSSOP-16	RU-16	1,000	5232BC

*Line 1 contains ADI logo symbol and the data code YYWW, line 2 contains detail model number listed in this column.

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AD5232

PIN CONFIGURATION

CLK				RDY
	1		16
SDI				CS
	2		15
SDO				PR
	3		14
GND		AD5232
	4		13	WP
VSS		TOP VIEW		VDD
	5	(Not to Scale)	12
A1				A2
	6		11
W1				W2
	7		10
B1				B2
	8		9

		PIN FUNCTION DESCRIPTIONS
Pin
Number	Mnemonic	Description
1	CLK	Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges.
2	SDI	Serial Data Input Pin. MSB Loaded First.
3	SDO	Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands 9 and 10
		activate the SDO output. See Table II. Other commands shift out the previously loaded SDI bit
		pattern delayed by 16 clock pulses. This allows daisy-chain operation of multiple packages.
4	GND	Ground Pin, Logic Ground Reference.
5	VSS	Negative Supply. Connect to zero volts for single supply applications.
6	A1	A Terminal of RDAC1
7	W1	Wiper Terminal of RDAC1, ADDR(RDAC1) = 0H
8	B1	B Terminal of RDAC1
9	B2	B Terminal of RDAC2
10	W2	Wiper Terminal of RDAC2, ADDR(RDAC2) = 1H
11	A2	A Terminal of RDAC2
12	VDD	Positive Power Supply Pin
13	WP	Write Protect Pin. When active low, WP prevents any changes to the present register contents, except
		PR and CMD 1 and 8 will refresh RDAC register from EEMEM. Execute a NOP instruction before
		returning WP to logic high.
14	PR	Hardware Override Preset Pin. Refreshes the scratch pad register with current contents of the EEMEM
		register. Factory default loads midscale 80H until EEMEM is loaded with a new value by the user
		(PR is activated at the logic high transition).
15	CS	Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.
16	RDY	Ready. Active-high open drain output, requires pull-up resistor. Identifies completion of commands
		2, 3, 8, 9, 10, and PR.

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