ANALOG DEVICES AD5623R, AD5643R, AD5663R Service Manual

	Dual 12-/14-/16-Bit nanoDAC® with
	5 ppm/°C On-Chip Reference
Data Sheet	AD5623R/AD5643R/AD5663R

FEATURES

Low power, smallest pin-compatible, dual nanoDAC AD5663R: 16 bits

AD5643R: 14 bits AD5623R: 12 bits

User-selectable external or internal reference External reference default

On-chip 1.25 V/2.5 V, 5 ppm/°C reference 10-lead MSOP and 3 mm × 3 mm LFCSP 2.7 V to 5.5 V power supply

Guaranteed monotonic by design Power-on reset to zero scale

Per channel power-down Serial interface up to 50 MHz

Hardware LDAC and CLR functions

APPLICATIONS

Process control

Data acquisition systems

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators

GENERAL DESCRIPTION

The AD5623R/AD5643R/AD5663R, members of the nanoDAC family, are low power, dual 12-, 14-, and 16-bit buffered voltageout digital-to-analog converters (DAC) that operate from a single 2.7 V to 5.5 V supply and are guaranteed monotonic by design.

The AD5623R/AD5643R/AD5663R have an on-chip reference. The AD5623R-3/AD5643R-3/AD5663R-3 have a 1.25 V, 5 ppm/°C reference, giving a full-scale output of 2.5 V; and the AD5623R-5/ AD5643R-5/AD5663R-5 have a 2.5 V, 5 ppm/°C reference, giving a full-scale output of 5 V. The on-chip reference is off at power-up, allowing the use of an external reference; and all devices can be operated from a single 2.7 V to 5.5 V supply. The internal reference is turned on by writing to the DAC.

The parts incorporate a power-on reset circuit that ensures the DAC output powers up to 0 V and remains there until a valid write takes place. The part contains a power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads while in powerdown mode.

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

FUNCTIONAL BLOCK DIAGRAM

			VDD	VREFIN/VREFOUT
		LDAC			1.25V/2.5V
					REFERENCE
SCLK		INPUT	DAC	STRING	BUFFER	VOUTA
		REGISTER	REGISTER	DAC A
SYNC	INTERFACE
	LOGIC
DIN		INPUT	DAC	STRING	BUFFER	VOUTB
		REGISTER	REGISTER	DAC B
		AD5623R/AD5643R/AD5663R
				POWER-ON	POWER-DOWN
				RESET	LOGIC
	LDAC	CLR	GND			05858-001

Figure 1.

Table 1. Related Devices

Part No.	Description
AD5663	2.7 V to 5.5 V, dual 16-bit nanoDAC, with external
	reference

The low power consumption of this part in normal operation makes it ideally suited to portable, battery-operated equipment.

The AD5623R/AD5643R/AD5663R use a versatile, 3-wire serial interface that operates at clock rates up to 50 MHz, and they are compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The on-chip precision output amplifier enables rail-to-rail output swing to be achieved.

PRODUCT HIGHLIGHTS

1.Dual 12-, 14-, and 16-bit DAC.

2.On-chip 1.25 V/2.5 V, 5 ppm/°C reference.

3.Available in 10-lead MSOP and 10-lead, 3 mm × 3 mm LFCSP.

4.Low power; typically consumes 0.6 mW at 3 V and 1.25 mW at 5 V.

5.4.5 µs maximum settling time for the AD5623R.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: [phone] www.analog.com Fax: [phone] ©2006–2012 Analog Devices, Inc. All rights reserved.

AD5623R/AD5643R/AD5663R

Data Sheet

TABLE OF CONTENTS
Features ..............................................................................................	1
Applications.......................................................................................	1
Functional Block Diagram ..............................................................	1
General Description .........................................................................	1
Product Highlights ...........................................................................	1
Revision History ...............................................................................	2
Specifications.....................................................................................	3
AD5623R-5/AD5643R-5/AD5663R-5.......................................	3
AD5623R-3/AD5643R-3/AD5663R-3.......................................	5
AC Characteristics........................................................................	6
Timing Characteristics ................................................................	7
Timing Diagram ...........................................................................	7
Absolute Maximum Ratings............................................................	8
ESD Caution..................................................................................	8
Pin Configuration and Function Descriptions.............................	9
Typical Performance Characteristics ...........................................	10
Terminology ....................................................................................	18
Theory of Operation ......................................................................	20
Digital-to-Analog Section .........................................................	20
Resistor String.............................................................................	20

Output Amplifier........................................................................	20
Internal Reference ......................................................................	20
External Reference .....................................................................	20
Serial Interface ............................................................................	20
Input Shift Register ....................................................................	21
SYNC Interrupt ..........................................................................	21
Power-On Reset..........................................................................	22
Software Reset.............................................................................	22
Power-Down Modes ..................................................................	22
LDAC Function ..........................................................................	23
Internal Reference Setup ...........................................................	24
Microprocessor Interfacing.......................................................	25
Applications Information ..............................................................	26
Using a Reference as a Power Supply.......................................	26
Bipolar Operation Using the AD5663R ..................................	26
Using the AD5663R with a Galvanically Isolated Interface . 26
Power Supply Bypassing and Grounding................................	27
Outline Dimensions .......................................................................	28
Ordering Guide ..........................................................................	29

REVISION HISTORY
4/12—Rev. D to Rev. C
Changes to Table 2............................................................................	3
Updated Outline Dimensions .......................................................	28
Changes to Ordering Guide ..........................................................	29
4/11—Rev. C to Rev. D
Changes to Ordering Guide ..........................................................	29
6/10—Rev. B to Rev. C
Changes to Ordering Guide ..........................................................	28

4/10—Rev. A to Rev. B
Updated Outline Dimensions.......................................................	28
12/06—Rev. 0 to Rev. A
Changes to Table 2.............................................................................	3
Changes to Table 3.............................................................................	5
Changes to Figure 3...........................................................................	9
Changes to Ordering Guide ..........................................................	28
4/06—Revision 0: Initial Version

Rev. E | Page 2 of 32

Data Sheet

AD5623R/AD5643R/AD5663R

SPECIFICATIONS

AD5623R-5/AD5643R-5/AD5663R-5

VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.

Table 2.

		A Grade1			B Grade1
Parameter	Min	Typ	Max	Min	Typ	Max	Unit	Conditions/Comments
STATIC PERFORMANCE2
AD5663R
Resolution				16			Bits
Relative Accuracy					±8	±16	LSB
Differential Nonlinearity						±1	LSB	Guaranteed monotonic by design
AD5643R
Resolution				14			Bits
Relative Accuracy					±2	±4	LSB
Differential Nonlinearity						±0.5	LSB	Guaranteed monotonic by design
AD5623R
Resolution				12			Bits
Relative Accuracy		±1	±2		±0.5	±1	LSB
Differential Nonlinearity			±1			±0.25	LSB	Guaranteed monotonic by design
Zero-Scale Error		+2	+10		+2	+10	mV	All 0s loaded to DAC register
Offset Error		±1	±10		±1	±10	mV
Full-Scale Error		−0.1	±1		−0.1	±1	% of	All 1s loaded to DAC register
							FSR
Gain Error			±1.5			±1.5	% of
							FSR
Zero-Scale Error Drift		±2			±2		µV/°C
Gain Temperature Coefficient		±2.5			±2.5		ppm	Of FSR/°C
DC Power Supply Rejection Ratio		−100			−100		dB	DAC code = midscale ; VDD = 5 V ±
								10%
DC Crosstalk (External Reference)		10			10		µV	Due to full-scale output change;
								RL = 2 kΩ to GND or VDD
		10			10		µV/mA	Due to load current change
		5			5		µV	Due to powering down (per channel)
DC Crosstalk (Internal Reference)		25			25		µV	Due to full-scale output change;
								RL = 2 kΩ to GND or VDD
		20			20		µV/mA	Due to load current change
		10			10		µV	Due to powering down (per channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range	0		VDD	0		VDD	V
Capacitive Load Stability		2			2		nF	RL = ∞
		10			10		nF	RL = 2 kΩ
DC Output Impedance		0.5			0.5		Ω
Short-Circuit Current		30			30		mA	VDD = 5 V
Power-Up Time		4			4		μs	Coming out of power-down mode;
								VDD = 5 V
REFERENCE INPUTS
Reference Current		170	200		170	200	µA	VREF = VDD = 5.5 V
Reference Input Range	0.75		VDD	0.75		VDD	V
Reference Input Impedance		26			26		kΩ

Rev. E | Page 3 of 32

AD5623R/AD5643R/AD5663R

Data Sheet

A Grade1

B Grade1

Parameter

Min

Typ

Max

Min

Typ

Max

Unit

Conditions/Comments

REFERENCE OUTPUT

Output Voltage

2.495

2.505

2.495

2.505

V

At ambient

Reference Temperature Coefficient3

±10

±5

±10

ppm/°C

MSOP package models

±10

±10

ppm/°C

LFCSP package models

Output Impedance

7.5

7.5

kΩ

LOGIC INPUTS3

Input Current

±2

±2

µA

All digital inputs

Input Low Voltage (VINL)

0.8

0.8

V

VDD = 5 V

Input High Voltage (VINH)

2

2

V

VDD = 5 V

Pin Capacitance

3

3

pF

DIN, SCLK, and

SYNC

19

19

pF

LDAC

and

CLR

POWER REQUIREMENTS

VDD

4.5

5.5

4.5

5.5

V

IDD (Normal Mode)4

VIH = VDD and VIL = GND

VDD = 4.5 V to 5.5 V

0.25

0.45

0.25

0.45

mA

Internal reference off

VDD = 4.5 V to 5.5 V

0.8

1

0.8

1

mA

Internal reference on

IDD (All Power-Down Modes)5

VDD = 4.5 V to 5.5 V

0.48

1

0.48

1

µA

VIH = VDD and VIL = GND

1Temperature range: A, B grade = −40°C to +105°C.

2Linearity calculated using a reduced code range: AD5663R (Code 512 to Code 65,024), AD5643R (Code 128 to Code 16,256), and AD5623R (Code 32 to Code 4064). Output unloaded.

3Guaranteed by design and characterization, not production tested.

4Interface inactive. All DACs active. DAC outputs unloaded.

5Both DACs powered down.

Rev. E | Page 4 of 32

Data Sheet	AD5623R/AD5643R/AD5663R

AD5623R-3/AD5643R-3/AD5663R-3

VDD = 2.7 V to 3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.

Table 3.

		B Grade1
Parameter	Min	Typ	Max	Unit	Conditions/Comments
STATIC PERFORMANCE2
AD5663R
Resolution	16			Bits
Relative Accuracy		±8	±16	LSB
Differential Nonlinearity			±1	LSB	Guaranteed monotonic by design
AD5643R
Resolution	14			Bits
Relative Accuracy		±2	±4	LSB
Differential Nonlinearity			±0.5	LSB	Guaranteed monotonic by design
AD5623R
Resolution	12			Bits
Relative Accuracy		±0.5	±1	LSB
Differential Nonlinearity			±0.25	LSB	Guaranteed monotonic by design
Zero-Scale Error		+2	+10	mV	All 0s loaded to DAC register
Offset Error		±1	±10	mV
Full-Scale Error		−0.1	±1	% of FSR	All 1s loaded to DAC register
Gain Error			±1.5	% of FSR
Zero-Scale Error Drift		±2		µV/°C
Gain Temperature Coefficient		±2.5		ppm	Of FSR/°C
DC Power Supply Rejection Ratio		−100		dB	DAC code = midscale; VDD = 3 V ± 10%
DC Crosstalk (External Reference)		10		µV	Due to full-scale output change;
					RL = 2 kΩ to GND or VDD
		10		µV/mA	Due to load current change
		5		µV	Due to powering down (per channel)
DC Crosstalk (Internal Reference)		25		µV	Due to full-scale output change;
					RL = 2 kΩ to GND or VDD
		20		µV/mA	Due to load current change
		10		µV	Due to powering down (per channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range	0		VDD	V
Capacitive Load Stability		2		nF	RL = ∞
		10		nF	RL = 2 kΩ
DC Output Impedance		0.5		Ω
Short Circuit Current		30		mA	VDD = 3 V
Power-Up Time		4		µs	Coming out of power-down mode; VDD = 3 V
REFERENCE INPUTS
Reference Current		170	200	µA	VREF = VDD = 3.6 V
Reference Input Range	0.75		VDD	V
Reference Input Impedance		26		kΩ
REFERENCE OUTPUT
Output Voltage	1.247		1.253	V	At ambient
Reference Temperature Coefficient3		±5	±15	ppm/°C	MSOP package models
		±10		ppm/°C	LFCSP package models
Output Impedance		7.5		kΩ

Rev. E | Page 5 of 32

AD5623R/AD5643R/AD5663R											Data Sheet
		B Grade1
Parameter	Min	Typ	Max	Unit	Conditions/Comments
LOGIC INPUTS3
Input Current			±2	µA		All digital inputs
VINL, Input Low Voltage			0.8	V		VDD = 3 V
VINH, Input High Voltage	2			V		VDD = 3 V
Pin Capacitance		3		pF		DIN, SCLK, and				SYNC
		19		pF
						LDAC	and	CLR
POWER REQUIREMENTS
VDD	2.7		3.6	V
IDD (Normal Mode)4						VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V		200	425	µA		Internal reference off
VDD = 2.7 V to 3.6 V		800	900	µA		Internal reference on
IDD (All Power-Down Modes)5
VDD = 2.7 V to 3.6 V		0.2	1	µA		VIH = VDD and VIL = GND

1Temperature range: B grade = −40°C to +105°C.

2Linearity calculated using a reduced code range: AD5663R (Code 512 to Code 65,024), AD5643R (Code 128 to Code 16,256), and AD5623R (Code 32 to Code 4064). Output unloaded.

3Guaranteed by design and characterization, not production tested.

4Interface inactive. All DACs active. DAC outputs unloaded.

5Both DACs powered down.

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.

Table 4.

Parameter1, 2	Min	Typ	Max	Unit	Conditions/Comments3
Output Voltage Settling Time
AD5623R		3	4.5	µs	¼ to ¾ scale settling to ±0.5 LSB
AD5643R		3.5	5	µs	¼ to ¾ scale settling to ±0.5 LSB
AD5663R		4	7	µs	¼ to ¾ scale settling to ±2 LSB
Slew Rate		1.8		V/µs
Digital-to-Analog Glitch Impulse		10		nV-s	1 LSB change around major carry
Digital Feedthrough		0.1		nV-s
Reference Feedthrough		−90		dB	VREF = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz
Digital Crosstalk		0.1		nV-s
Analog Crosstalk		1		nV-s	External reference
		4		nV-s	Internal reference
DAC-to-DAC Crosstalk		1		nV-s	External reference
		4		nV-s	Internal reference
Multiplying Bandwidth		340		kHz	VREF = 2 V ± 0.1 V p-p
Total Harmonic Distortion		−80		dB	VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz
Output Noise Spectral Density		120		nV/√Hz	DAC code = midscale, 1 kHz
		100		nV/√Hz	DAC code = midscale, 10 kHz
Output Noise		15		μV p-p	0.1 Hz to 10 Hz

1Guaranteed by design and characterization, not production tested.

2See the Terminology section.

3Temperature range: A, B grade = −40°C to +105°C, typical at +25°C.

Rev. E | Page 6 of 32

Data Sheet	AD5623R/AD5643R/AD5663R

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.1

Table 5.

Limit at TMIN, TMAX

Parameter

VDD = 2.7 V to 5.5 V

Unit

Conditions/Comments

t12

20

ns min

SCLK cycle time

t2

9

ns min

SCLK high time

t3

9

ns min

SCLK low time

to SCLK falling edge setup time

t4

13

ns min

SYNC

t5

5

ns min

Data setup time

t6

5

ns min

Data hold time

rising edge

t7

0

ns min

SCLK falling edge to

SYNC

t8

15

ns min

Minimum

SYNC

high time

rising edge to SCLK fall ignore

t9

13

ns min

SYNC

fall ignore

t10

0

ns min

SCLK falling edge to

SYNC

t11

10

ns min

LDAC

pulse width low

t12

15

ns min

SCLK falling edge to

LDAC

rising edge

t13

5

ns min

CLR

pulse width low

t14

0

ns min

SCLK falling edge to

LDAC

falling edge

t15

300

ns max

CLR

pulse activation time

1Guaranteed by design and characterization, not production tested.

2Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.

TIMING DIAGRAM

t10			t1		t9
SCLK
t8	t4	t3		t2	t7
SYNC
		t6
		t5
DIN	DB23				DB0
					t11
					t14
LDAC1
					t12

LDAC2

					t13
	CLR
VOUT							t15

1ASYNCHRONOUS LDAC UPDATE MODE.

2SYNCHRONOUS LDAC UPDATE MODE.

Figure 2. Serial Write Operation

05858-002

Rev. E | Page 7 of 32

AD5623R/AD5643R/AD5663R

Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 6.

Parameter	Rating
VDD to GND	−0.3 V to +7 V
VOUT to GND	−0.3 V to VDD + 0.3 V
VREFIN/VREFOUT to GND	−0.3 V to VDD + 0.3 V
Digital Input Voltage to GND	−0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial	−40°C to +105°C
Storage Temperature Range	−65°C to +150°C
Junction Temperature (TJ max)	150°C
Power Dissipation	(TJ max − TA)/θJA
LFCSP Package (4-Layer Board)
θJA Thermal Impedance	61°C/W
MSOP Package (4-Layer Board)
θJA Thermal Impedance	142°C/W
θJC Thermal Impedance	43.7°C/W
Reflow Soldering Peak Temperature
Pb-Free	260(+0/−5)°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. E | Page 8 of 32

Data Sheet

AD5623R/AD5643R/AD5663R

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VOUTA									VREFIN/VREFOUT
						1	AD5623R/	10
VOUTB						2		9	VDD
	GND						AD5643R/		DIN
						3	AD5663R	8
	LDAC					4	TOP VIEW	7	SCLK
							(Not to Scale)
		CLR				5		6		SYNC
												003-
	NOTE:
	EXPOSED PAD TIED TO GND ON											05858
	LFCSP PACKAGE.

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VOUTA

Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

2

VOUTB

Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

3

GND

Ground. Reference point for all circuitry on the part.

4

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.

LDAC

This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.

5

Asynchronous Clear Input. The

input is falling edge sensitive. While

is low, all

pulses are

CLR

CLR

CLR

LDAC

ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V.

The part exits clear code mode on the 24th falling edge of the next write to the part. If CLR is activated during

a write sequence, the write is aborted.

6

Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data.

SYNC

When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the

following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge,

in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.

7

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.

Data can be transferred at rates up to 50 MHz.

8

DIN

Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge

of the serial clock input.

9

VDD

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with

a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.

10

VREFIN/VREFOUT

Common Reference Input/Reference Output. When the internal reference is selected, this is the reference output

pin. When using an external reference, this is the reference input pin. The default for this pin is a reference input.

Rev. E | Page 9 of 32

AD5623R/AD5643R/AD5663R

TYPICAL PERFORMANCE CHARACTERISTICS

10

VDD = VREF = 5V

8

TA = 25°C

6

(LSB)

4

2

ERROR

0

INL

–2

–4

–6

–8

–10

-005

0

5k

10k

15k

20k

25k 30k

35k

40k

45k

50k

55k

60k 65k

05858

CODE

Figure 4. INL—AD5663R, External Reference

4

VDD

= VREF = 5V

3

TA = 25°C

(LSB)

2

1

ERROR

0

INL

–1

–2

–3

–4

-006

0

2.5k

5.0k

7.5k

10.0k

12.5k

15.0k

05858

CODE

Figure 5. INL—AD5643R, External Reference

1.0

VDD = VREF = 5V

0.8

TA = 25°C

0.6

(LSB)

0.4

0.2

ERROR

0

INL

–0.2

–0.4

–0.6

–0.8

–1.0

-007

0

0.5k

1.0k

1.5k

2.0k

2.5k

3.0k

3.5k

4.0k

05858

CODE

Figure 6. INL—AD5623R, External Reference

Data Sheet

	1.0		VDD = VREF = 5V
	0.8		TA = 25°C
	0.6
(LSB)	0.4
	0.2
ERROR	0
DNL	–0.2
	–0.4
	–0.6
	–0.8
	–1.0 0		10k		20k	30k	40k	50k		60k	-008
						CODE					05858
			Figure 7. DNL—AD5663R, External Reference
	0.5		VDD = VREF = 5V
	0.4		TA = 25°C
	0.3
(LSB)	0.2
	0.1
ERROR	0
DNL	–0.1
	–0.2
	–0.3
	–0.4										-009
	–0.5	0	2.5k		5.0k	7.5k	10.0k	12.5k		15.0k	05858
						CODE
			Figure 8. DNL—AD5643R, External Reference
	0.20 VDD = VREF = 5V
	0.15	TA = 25°C
(LSB)	0.10
	0.05
ERROR
	0
DNL	–0.05
	–0.10
	–0.15
	–0.20	0	0.5k	1.0k	1.5k	2.0k	2.5k	3.0k	3.5k	4.0k	-010
											05858
						CODE

Figure 9. DNL—AD5623R, External Reference

Rev. E | Page 10 of 32