Analog Devices AD5542, AD5541 Datasheet

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Analog Devices AD5542, AD5541 Datasheet

a

5 V, Serial-Input

Voltage-Output, 16-Bit DACs

 

 

 

 

 

AD5541/AD5542

 

 

 

FEATURES

Full 16-Bit Performance

5 V Single Supply Operation Low Power

Short Settling Time

Unbuffered Voltage Output Capable of Driving 60 kV

Loads Directly SPI™/QSPI™/MICROWIRE™-Compatible Interface

Standards

Power-On Reset Clears DAC Output to 0 V (Unipolar Mode)

Schmitt Trigger Inputs for Direct Optocoupler Interface

APPLICATIONS

Digital Gain and Offset Adjustment

Automatic Test Equipment

Data Acquisition Systems

Industrial Process Control

GENERAL DESCRIPTION

The AD5541 and AD5542 are single, 16-bit, serial input, voltage output DACs that operate from a single 5 V ± 10% supply.

The AD5541 and AD5542 utilize a versatile 3-wire interface that is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards.

These DACs provide 16-bit performance without any adjustments. The DAC output is unbuffered, which reduces power consumption and offset errors contributed to by an output buffer.

The AD5542 can be operated in bipolar mode generating a

± VREF output swing. The AD5542 also includes Kelvin sense connections for the reference and analog ground pins to reduce layout sensitivity.

The AD5541 and AD5542 are available in an SO package.

FUNCTIONAL BLOCK DIAGRAMS

VDD

 

AD5541

 

REF

16-BIT DAC

VOUT

 

 

AGND

CS

16-BIT DATA LATCH

 

DIN

CONTROL

 

 

 

SCLK

LOGIC

 

SERIAL INPUT REGISTER

 

 

 

 

DGND

 

VDD

 

AD5542

RFB

 

RINV

RFB

 

INV

 

 

REFF

 

 

 

16-BIT DAC

VOUT

REFS

 

 

 

 

AGNDF

CS

16-BIT DATA LATCH

 

LDAC

CONTROL

 

 

AGNDS

SCLK

LOGIC

 

 

DIN

SERIAL INPUT REGISTER

 

 

 

DGND

 

PRODUCT HIGHLIGHTS

1.Single Supply Operation.

The AD5541 and AD5542 are fully specified and guaranteed for a single 5 V ± 10% supply.

2.Low Power Consumption.

These parts consume typically 1.5 mW with a 5 V supply.

3.3-Wire Serial Interface.

4.Unbuffered output capable of driving 60 kΩ loads.

This reduces power consumption as there is no internal buffer to drive.

5.Power-On Reset circuitry.

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corporation.

REV. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1999

AD5541/AD5542–SPECIFICATIONS

(VDD = 5 V 6 10%, VREF = 2.5 V, AGND = DGND = 0 V. All specifications

TA = TMIN to TMAX, unless otherwise noted.)

Parameter

Min Typ

Max

 

Unit

Test Condition

 

 

 

 

 

 

STATIC PERFORMANCE

 

 

 

 

 

Resolution

16

 

 

Bits

 

Relative Accuracy, INL

± 0.5

± 1.0

 

LSB

L, C Grades

 

± 0.5

± 2.0

 

LSB

B, J Grades

 

± 0.5

± 4.0

 

LSB

A Grade

Differential Nonlinearity

± 0.5

± 1.0

 

LSB

Guaranteed Monotonic

 

 

± 1.5

 

LSB

J Grade

Gain Error

–1.5

± 5

 

LSB

TA = 25°C

 

 

± 7

 

LSB

 

Gain Error Temperature Coefficient

± 0.1

± 1

 

ppm/°C

TA = 25°C

Zero Code Error

0.3

 

LSB

 

 

± 2

 

LSB

 

Zero Code Temperature Coefficient

± 0.05

 

 

ppm/°C

 

AD5542

 

 

 

Ω/Ω

RFB/RINV, Typically RFB = RINV = 28 kΩ

Bipolar Resistor Matching

1.000

± 0.0076

 

 

± 0.0015

 

%

Ratio Error

Bipolar Zero Offset Error

± 1

± 5

 

LSB

TA = 25°C

 

 

± 7

 

LSB

 

Bipolar Zero Temperature Coefficient

± 0.2

 

 

ppm/°C

 

 

 

 

 

 

 

OUTPUT CHARACTERISTICS

 

 

 

 

 

Output Voltage Range

0

VREF – 1 LSB

V

Unipolar Operation

 

–VREF

VREF – 1 LSB

V

AD5542 Bipolar Operation

Output Voltage Settling Time

1

 

 

µs

to 1/2 LSB of FS, CL = 10 pF

Slew Rate

25

 

 

V/µs

CL = 10 pF, Measured from 0% to 63%

Digital-to-Analog Glitch Impulse

10

 

 

nV-s

1 LSB Change Around the Major Carry

Digital Feedthrough

10

 

 

nV-s

All 1s Loaded to DAC, VREF = 2.5 V

DAC Output Impedance

6.25

 

 

kΩ

Tolerance Typically 20%

Power Supply Rejection Ratio

 

± 1.0

 

LSB

VDD ± 10%

DAC REFERENCE INPUT

 

 

 

 

 

Reference Input Range

2.0

VDD

 

V

 

Reference Input Resistance2

9

 

 

kΩ

Unipolar Operation

 

7.5

 

 

kΩ

AD5542, Bipolar Operation

 

 

 

 

 

 

LOGIC INPUTS

 

± 1

 

µA

 

Input Current

 

 

 

VINL, Input Low Voltage

 

0.8

 

V

 

VINH, Input High Voltage

2.4

 

 

V

 

Input Capacitance3

 

10

 

pF

 

Hysteresis Voltage3

0.4

 

 

V

 

REFERENCE

 

 

 

 

 

Reference –3 dB Bandwidth

1.3

 

 

MHz

All 1s Loaded

Reference Feedthrough

1

 

 

mV p-p

All 0s Loaded, VREF = 1 V p-p at 100 kHz

Signal-to-Noise Ratio

92

 

 

dB

 

Reference Input Capacitance

75

 

 

pF

Code 0000 Hex

 

120

 

 

pF

Code FFFF Hex

 

 

 

 

 

 

POWER REQUIREMENTS

 

 

 

 

 

VDD

4.50

5.50

 

V

 

IDD

0.3

1.1

 

mA

 

Power Dissipation

1.5

6.05

 

mW

 

 

 

 

 

 

 

NOTES

1Temperature ranges are as follows: A, B, C Versions: –40°C to +85°C. J, L Versions: 0°C to 70°C. 2Reference input resistance is code-dependent, minimum at 8555 hex.

3Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

–2–

REV. A

 

 

 

 

AD5541/AD5542

 

 

 

 

 

 

1, 2

(VDD = 5 V 6 5%, VREF = 2.5 V, AGND = DGND = 0 V. All specifications TA = TMIN to TMAX, unless

TIMING CHARACTERISTICS

otherwise noted.)

 

 

Limit at TMIN, TMAX

 

 

Parameter

All Versions

 

Unit

Description

 

 

 

 

 

fSCLK

25

 

MHz max

SCLK Cycle Frequency

t1

40

 

ns min

SCLK Cycle Time

t2

20

 

ns min

SCLK High Time

t3

20

 

ns min

SCLK Low Time

t4

15

 

ns min

CS Low to SCLK High Setup

t5

15

 

ns min

CS High to SCLK High Setup

t6

35

 

ns min

SCLK High to CS Low Hold Time

t7

20

 

ns min

SCLK High to CS High Hold Time

t8

15

 

ns min

Data Setup Time

t9

0

 

ns min

Data Hold Time

t10

30

 

ns min

LDAC Pulsewidth

t11

30

 

ns min

CS High to LDAC Low Setup

t12

30

 

ns min

CS High Time Between Active Periods

NOTES

1Guaranteed by design. Not production tested.

2Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

Specifications subject to change without notice.

 

 

 

t1

 

SCLK

 

 

 

 

 

t6

t2

t3

t5

 

t4

 

 

t7

CS

t12

 

 

 

 

 

 

 

 

t8

t9

 

 

 

 

 

 

DIN

DB15

 

 

DB0

t11

t10

LDAC*

*AD5542 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.

Figure 1. Timing Diagram

REV. A

–3–

AD5541/AD5542

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C unless otherwise noted)

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V Digital Input Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V

VOUT to AGND . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V AGND, AGNDF, AGNDS to DGND . . . . . –0.3 V to +0.3 V

Input Current to Any Pin Except Supplies . . . . . . . . ± 10 mA Operating Temperature Range

Industrial (A, B, C Versions) . . . . . . . . . . . –40°C to +85°C Commercial (J, L Versions) . . . . . . . . . . . . . . . 0°C to 70°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature, (TJ max)

. . . . . . . . . 150°C

Package Power Dissipation . . . . . . . . . . . . .

(TJ max – TA)/θJA

Thermal Impedance θJA

149.5°C/W

SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . .

SOIC (R-14) . . . . . . . . . . . . . . . . . . . . . .

. . . . 104.5°C/W

Lead Temperature, Soldering

215°C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . .

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . .

. . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model

INL

DNL

Temperature Range

Package Description

Package Option

 

 

 

 

 

 

AD5541CR

± 1 LSB

± 1 LSB

–40°C to +85°C

8-Lead Small Outline IC

SO-8

AD5541LR

± 1 LSB

± 1 LSB

0°C to 70°C

8-Lead Small Outline IC

SO-8

AD5541BR

± 2 LSB

± 1 LSB

–40°C to +85°C

8-Lead Small Outline IC

SO-8

AD5541JR

± 2 LSB

± 1.5 LSB

0°C to 70°C

8-Lead Small Outline IC

SO-8

AD5541AR

± 4 LSB

± 1 LSB

–40°C to +85°C

8-Lead Small Outline IC

SO-8

AD5542CR

± 1 LSB

± 1 LSB

–40°C to +85°C

14-Lead Small Outline IC

R-14

AD5542LR

± 1 LSB

± 1 LSB

0°C to 70°C

14-Lead Small Outline IC

R-14

AD5542BR

± 2 LSB

± 1 LSB

–40°C to +85°C

14-Lead Small Outline IC

R-14

AD5542JR

± 2 LSB

± 1.5 LSB

0°C to 70°C

14-Lead Small Outline IC

R-14

AD5542AR

± 4 LSB

± 1 LSB

–40°C to +85°C

14-Lead Small Outline IC

R-14

Die Size = 80 × 139 = 11,120 sq mil; Number of Transistors = 1,230.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5541/AD5542 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. A

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