Analog Devices AD53500 Datasheet

a		High Speed, High Current
		Capability Pin Driver
		AD53500

FEATURES

–2 V to +6 V Output Range 2.5 V Output Resistance

2.5 ns Tr/Tf for a 3 V Step

300 MHz Toggle Rate

Can Drive 25 V Lines and Lower

Peak Dynamic Current Capability of 400 mA Inhibit Leakage <1 mA

On-Chip Temperature Sensor

APPLICATIONS

Automatic Test Equipment

Semiconductor Test Systems

Board Test Systems

Instrumentation and Characterization Equipment

FUNCTIONAL BLOCK DIAGRAM

	VCC	VCC	VEE	VEE
				39nF	39nF
VH
DATA				VHDCPL
DATA	DRIVER		2V	VOUT
INH
INH
VL				VLDCPL
				TVCC
AD53500				THERM
				1.0mA/K
GND	GND	GND	GND	GND

PRODUCT DESCRIPTION:

The AD53500 is a complete high speed driver designed for use in digital or mixed signal test systems where high speed and high output drive capabilities are needed. Combining a high speed monolithic process and a unique surface mount package, this product attains superb electrical performance while preserving optimum packing densities and long-term reliability thanks to an ultrasmall 20-lead, PSOP package with built-in heat sink.

High and low reference levels can be set within a –2 V to +6 V range with low offset voltage and high gain accuracy. A 2.5 Ω output resistance allows use of an external backmatch resistor for application to 50 Ω, 25 Ω or other complex impedance load requirements. Without a backmatch resistor it is also capable of driving highly capacitive loads, typically achieving a rise/fall time

of less than 10 ns with a 1000 pF capacitance. To test I/O devices, the pin driver can be switched into a high impedance state (Inhibit Mode), electrically removing the driver from the path. The pin driver leakage current in inhibit is typically less than 1 µA and output capacitance is typically less than 18 pF.

Transitions from HI/LO or to inhibit are controlled through the data and inhibit inputs. The input circuitry utilizes high-speed differential inputs with a common-mode range of –2 V to +5 V. This allows for direct interface to the precision of differential ECL timing or the simplicity of stimulating the pin driver from a single-ended CMOS or TTL logic source or any combination over the common-mode range. The analog logic HI/LO inputs are equally easy to interface, typically requiring 50 µA of bias current.

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Fax: [phone]	© Analog Devices, Inc., 1999

AD53500–SPECIFICATIONS (All specifications are at TJ = +858C 6 58C, +VS = +10 V 6 3%, –VS = +6 V 6 3% unless otherwise noted. All temperature coefficients are measured over TJ = 758C–958C). (In test figures, voltmeter loading is 1 MV or greater, scope probe loading is 100 kV in parallel with 5 pF.) 39 nF capacitors must be connected between VCC and VHDCPL and between VEE and VLDCPL.

Parameter	Min	Typ	Max	Units	Test Conditions
DIFFERENTIAL INPUT CHARACTERISTICS
(DATA to DATA, INH to INH)
Common-Mode Input Voltage	–2		+5	Volts
Differential Input Range	ECL or TTL				ECL = –0.8 V/–1.8 V, TTL = 0 V/5 V
Bias Current		± 100		µA	VCM = –2 V, +5 V
REFERENCE INPUTS				µA
Bias Currents	–50		+50		VL, VH = 5 V
OUTPUT CHARACTERISTICS
Logic High Range	+1		+6	Volts	DATA = H, VL = –2 V, VH = +1 V to +6 V
Logic Low Range	–2		+2	Volts	DATA = L, VL = –2 V to +2 V, VH = +6 V
Amplitude (VH and VL)	0.1		8	Volts	VL = –0.05 V, VH = +0.05 V and
					VL = –2 V, VH = +6 V
VH, VL Interaction	–10		+10	mV	100 mV Output Amplitude
Absolute Accuracy
VH Offset	–100	± 0.3 ±5	+100	mV	DATA = H, VH = 0 V, VL = –2 V
VH Gain + Linearity Error				% of VH + mV	DATA = H, VL = –2 V, VH = +1 V to +6 V
VL Offset	–100	± 0.3 ±5	+100	mV	DATA = L, VL = 0 V, VH = +6 V
VL Gain + Linearity Error				% of VL + mV	DATA = L, VL = –2 V to +2 V, VH = +6 V
Offset TC, VH or VL		0.5		mV/°C	VL, VH = 0 V, +5 V and –2 V, 0 V
Output Resistance	1.5	2.5	5.5	Ω	VH = +3 V, VL = 0 V, IOUT = 0, –30 mA,
					+30 mA
Dynamic Current Limit		400		mA	CBYP = 39 nF, VH = +5 V, VL = 0 V
					CLOAD = 1000 pF, Tr/Tf = 10 ns
Static Current Limit	60		180	mA	Output to –2 V, VH = +6 V, VL = –1 V,
	–180		–60	mA	DATA = H and Output to +6 V, VH = +6 V,
					VL = –2 V, DATA = L
DYNAMIC PERFORMANCE, DRIVE
(VH and VL)					Measured at 50%, VH = +400 mV,
Propagation Delay Time		2.5		ns
				ps/°C	VL = –400 mV
Propagation Delay TC		1			Measured at 50%, VH = +400 mV,
					VL = –400 mV
Delay Matching, Edge-to-Edge		100		ps	Measured at 50%, VH = +400 mV,
Rise and Fall Time					VL = –400 mV
1 V Swing		0.85		ns	Measured 20%–80%, VL = 0 V, VH = 1 V
3 V Swing		2.5		ns	Measured 10%–90%, VL = 0 V, VH = 3 V
5 V Swing		4.0		ns	Measured 10%–90%, VL = 2 V, VH = 3 V
Rise and Fall Time TC		± 1		ps/°C
1 V Swing					Measured 20%–80%, VL = 0 V, VH = 1 V
3 V Swing		± 2		ps/°C	Measured 10%–90%, VL = 0 V, VH = 3 V
5 V Swing		± 3		ps/°C	Measured 10%–90%, VL = 0 V, VH = 5 V
Overshoot, Undershoot and Preshoot		+5.0 +30		% of Step + mV	VH–VL = 0.5 V, 1 V, 3 V, 8 V
Settling Time
to 15 mV		40		ns	VL = 0 V, VH = 0.5 V
to 4 mV		8		µs	VL = 0 V, VH = 0.5 V
Delay Change vs. Pulsewidth		100		ps	VL = 0 V, VH = 2 V, Pulsewidth = 2.5 ns/
					Period = 10 ns and Pulsewidth = 30 ns/
					Period = 120 ns
Minimum Pulsewidth
3 V Swing		3.8		ns	VL = 0 V, VH = 3 V, Output = 2.7 V p-p,
					Measure at 50%
5 V Swing		5.5		ns	VL = 0 V, VH = 5 V, Output = 4.5 V p-p,
					Measure at 50%
Toggle Rate		300		MHz	VL = –1.8 V, VH = –0.8 V, VOUT > 600 mV p-p

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					AD53500
Parameter	Min	Typ	Max	Units	Test Conditions
DYNAMIC PERFORMANCE, INHIBIT
Delay Time, Active to Inhibit	2		10	ns	Measured at 50%, VH = +2 V,
					VL = –2 V, 50 Ω Terminated to Ground
Delay Time, Inhibit to Active	2		10	ns	Measured at 50%, VH = +2 V,
					VL = –2 V, 50 Ω Terminated to Ground
I/O Spike		<200		mV, p-p	VH = 0 V, VL = 0 V
Output Leakage	–1.0		+1.0	µA	VOUT = –2 V to +6 V
Output Capacitance		18		pF	Driver Inhibited
PSRR, Drive Mode		35		dB	VS = VS ± 3%
POWER SUPPLIES
Total Supply Range		16		V
Positive Supply		+10		V
Negative Supply		–6		V
Positive Supply Current		85	95	mA
Negative Supply Current		88	98	mA
Total Power Dissipation		1.37	1.54	W
Temperature Sensor Gain Factor		1.0		µA/K	RLOAD = 10 kΩ, VSOURCE = +10 V

NOTES

Connecting or shorting the decoupling capacitors to ground will result in the destruction of the device.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS1

Power Supply Voltage

+VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +11 V –VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V +VS to –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +18 V

Inputs
DATA, DATA, INH, INH . . . . . . . . . . . . . . . .	+5 V, –3 V
DATA to DATA, INH to INH . . . . . . . . . . .	. . . . . ±3 V
VH, VL to GND . . . . . . . . . . . . . . . . . . . . . . . . .	+7 V, –3 V
VH to VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	+10 V, 0 V

Outputs

VOUT Short Circuit Duration to Ground . . . . . . . Indefinite2

VOUT Range in Inhibit Mode . . . . . . . . . . . . . See Figure 1 VHDCPL . . . . . . . . Do Not Connect Except for Cap to VCC3 VLDCPL . . . . . . . . . Do Not Connect Except for Cap to VEE3 THERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VS, 0 V

Environmental

Operating Temperature (Junction) . . . . . . . . . . . . . .+175°C Storage Temperature . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec)4 . . . . . . . . . .+260°C

VOUT

										VOUT = (MAX) = +7V
					7
						6
						5
						4
						3
						2
						1												VH, VL
–2			–1		1					2	3		4	5		6
							–1
							–2
							–3

VOUT = (MIN) = –3V

FIGURE 1 SHOWS THE MAXIMUM ALLOWABLE LIMITS FOR VOUT AS A FUNCTION

OF VHIGH AND VLOW WHEN THE DRIVER IS OPERATING IN INHIBIT MODE. THE LIMITS, AS STATED BEFORE, ARE MAXIMUM RATINGS ONLY, AND SHOULD NOT

BE USED AS THE PART'S NORMAL OPERATING RANGE. THIS RANGE APPLIES

ONLY TO SUPPLIES OF +V = +10V AND –V = –6V AND SHOULD BE DERATED

S S

PROPORTIONALLY FOR LOWER SUPPLIES.

NOTES

1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Absolute maximum limits apply individually, not in combination. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2Output short circuit protection is guaranteed as long as proper heat sinking is employed to ensure compliance with the operating temperature limits.

3The VHDCPL and VLDCPL capacitors may be replaced by a low value resistor for higher dc-current drive capability.

4To ensure lead coplanarity (±0.002 inches) and solderability, handling with bare hands should be avoided and the device should be stored in environments at 24°C

± 5°C (75°F ± 10°F) with relative humidity not to exceed 65%.

VHIGH / VLOW

Figure 1. Absolute Maximum Ratings for VOUT

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD53500 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

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