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a
SamplePort Stereo Asynchronous
Sample Rate Converters
AD1890/AD1891
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700Fax: 617/326-8703
FEATURES
Automatically Sense Sample Frequencies—No
Programming Required
Tolerant of Sample Clock Jitter
Smooth Transition When Sample Clock Frequencies
Cross
Accommodate Dynamically Changing Asynchronous
Sample Clocks
8 kHz to 56 kHz Sample Clock Frequency Range
1:2 to 2:1 Ratio Between Sample Clocks
–106 dB THD+N at 1 kHz (AD1890)
120 dB Dynamic Range (AD1890)
Optimal Clock Tracking Control
–Short/Long Group Delay Modes
–Slow/Fast Settling Modes
Linear Phase in All Modes
Equivalent of 4 Million 22-Bit FIR Filter Coefficients
Stored On-Chip
Automatic Output Mute
Flexible Four Wire Serial Interfaces
Low Power
APPLICATIONS
Digital Mixing Consoles and Digital Audio Workstations
CD-R, DAT, DCC and MD Recorders
Multitrack Digital Audio and Video Tape Recorders
Studio to Transmitter Links
Digital Audio Signal Routers/Switches
Digital Audio Broadcast Equipment
High Quality D/A Converters
Digital Tape Recorder Varispeed Applications
Computer Communication and Multimedia Systems
PRODUCT OVERVIEW
The AD1890 and AD1891 SamplePorts™ are fully digital, stereo
Asynchronous Sample Rate Converters (ASRCs) that solve sample
rate interfacing and compatibility problems in digital audio equip-
ment. Conceptually, these converters interpolate the input data up
to a very high internal sample rate with a time resolution of 300 ps,
then decimate down to the desired output sample rate. The
AD1890 is intended for 18- and 20-bit professional applications,
and the AD1891 is intended for 16-bit lower cost applications
where large dynamic sample-rate changes are not encountered.
These devices are asynchronous because the frequency and phase
relationships between the input and output sample clocks (both are
inputs to the AD1890/AD1891 ASRCs) are arbitrary and need not
be related by a simple integer ratio. There is no need to explicitly
select or program the input and output sample clock frequencies, as
the AD1890/AD1891 automatically sense the relationship between
SamplePort and SamplePorts are trademarks of Analog Devices, Inc.
the two clocks. The input and output sample clock frequencies
can nominally range from 8 kHz to 56 kHz, and the ratio
between them can vary from 1:2 to 2:1.
The AD1890/AD1891 use multirate digital signal processing
techniques to construct an output sample stream from the input
sample stream. The input word width is 4 to 20 bits for the
AD1890 or 4 to 16 bits for the AD1891. Shorter input words
are automatically zero-filled in the LSBs. The output word
width for both devices is 24 bits. The user can receive as many
of the output bits as desired. Internal arithmetic is performed
with 22-bit coefficients and 27-bit accumulation. The digital
samples are processed with unity gain.
The input and output control signals allow for considerable flex-
ibility for interfacing to a variety of DSP chips, AES/EBU
receivers and transmitters and for I
2
S compatible devices. Input
and output data can be independently justified to the left/right
clock edge, or delayed by one bit clock from the left/right clock
edge. Input and output data can also be independently justified
to the word clock rising edge or delayed by one bit clock from
the word clock rising edge. The bit clocks can also be indepen-
dently configured for rising edge active or falling edge active
operation.
The AD1890/AD1891 SamplePort™ ASRCs have on-chip digi-
tal coefficients that correspond to a highly oversampled 0 kHz to
20 kHz low-pass filter with a flat passband, a very narrow tran-
sition band, and a high degree of stopband attenuation. A subset
of these filter coefficients are dynamically chosen on the basis of
the filtered instantaneous ratio between the input sample clock
(L
R_I) and the output sample clock (LR_O), and these coeffi-
cients are used in an FIR convolver to perform the sample rate
conversion. Refer to the “Theory of Operation” section of this
data sheet for a more thorough functional description. The low-
pass filter has been designed so that full 20 kHz bandwidth is
maintained when the input and output sample clock frequencies
are as low as 44.1 kHz. If the output sample rate drops below
the input sample rate, the bandwidth of the input signal is
(continued on Page 4)
AD1890/AD1891–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltage+5.0V
Ambient Temperature25°C
MCLK20MHz
Load Capacitance100pF
All minimums and maximums tested except as noted.
PERFORMANCE (Guaranteed over 0°C ≤ T
A
≤ 70°C, V
DD
= 5.0 V ± 10%, 8 MHz ≤ MCLK ≤ 20 MHz)
MinMaxUnits
AD1890 Dynamic Range (20 Hz to 20 kHz, –60 dB Input)†120dB
AD1891 Dynamic Range (20 Hz to 20 kHz, –60 dB Input)†96dB
Total Harmonic Distortion + Noise†dB
AD1890 and AD1891 (20 Hz to 20 kHz, Full-Scale Input,
F
SOUT
/F
SIN
Between 0.5 and 2.0)–94dB
AD1890 (1 kHz Full-Scale Input, F
SOUT
/F
SIN
Between 0.7 and 1.4)–106dB
AD1890 (10 kHz Full-Scale Input, F
SOUT
/F
SIN
Between 0.7 and 1.4)–100dB
AD1891 (1 kHz Full-Scale Input, F
SOUT
/F
SIN
Between 0.7 and 1.4)–96dB
AD1891 (10 kHz Full-Scale Input, F
SOUT
/F
SIN
Between 0.7 and 1.4)–95dB
Interchannel Phase Deviation†0Degrees
Input and Output Sample Clock Jitter†10ns
(For
≤
1 dB Degradation in THD+N with 10 kHz Full-Scale Input, Slow-Settling Mode)
DIGITAL INPUTS (Guaranteed over 0°C ≤ T
A
≤ 70°C, V
DD
= 5.0 V ± 10%, 8 MHz ≤ MCLK ≤ 20 MHz)
MinMaxUnits
V
IH
2.2V
V
IL
0. 8V
I
IH
@ V
IH
= +5 V4µA
I
IL
@ V
IL
= 0 V4µA
V
OH
@ I
OH
= –4 mA3.6V
V
OL
@ I
OL
= 4 mA0.4V
Input Capacitance†15pF
DIGITAL TIMING (Guaranteed over 0°C ≤ T
A
≤ 70°C, V
DD
= 5.0 V ± 10%, 8 MHz ≤ MCLK ≤ 20 MHz)
MinMaxUnits
t
MCLK
MCLK Period50125ns
f
MCLK
MCLK Frequency (1/t
MCLK
)820MHz
t
MPWL
MCLK LO Pulse Width20ns
t
MPWH
MCLK HI Pulse Width20ns
f
LRI
LR_I Frequency with 20 MHz MCLK†1070kHz
t
RPWL
RESET LO Pulse Width100ns
t
RS
RESET Setup to MCLK Falling15ns
t
BCLK
BCLK_I/O Period†80ns
f
BCLK
BCLK_I/O Frequency (l/t
BCLK
)†12.5MHz
t
BPWL
BCLK_I/O LO Pulse Width40ns
t
BPWH
BCLK_I/O HI Pulse Width40ns
t
WSI
WCLK_I Setup to BCLK_I15ns
t
WSO
WCLK_O Setup to BCLK_O30ns
t
LRSI
LR_I Setup to BCLK_I15ns
t
LRSO
LR_O Setup to BCLK_O30ns
t
DS
Data Setup to BCLK_I0ns
t
DH
Data Hold from BCLK_I25ns
t
DPD
Data Propagation Delay from BCLK_O40ns
t
DOH
Data Output Hold from BCLK_O5ns
REV. 0
–2–
AD1890/AD1891
REV. 0
–3–
POWER (0°C ≤ T
A
≤ 70°C, MCLK = 16 MHz, F
SIN
= 48 kHz, F
SOUT
= 44.1 kHz)
MinTypMaxUnits
Supplies
Voltage, V
DD
2.75.5V
Current, I
DD
(V
DD
= 5.0 V)3540mA
Current, I
DD
(V
DD
= 3.0 V)19mA
Dissipation
Operation (V
DD
= 5.0 V)175200mW
Operation (V
DD
= 3.0 V)57mW
TEMPERATURE RANGE
MinMaxUnits
Specifications Guaranteed0+70°C
Operation Guaranteed–40+85°C
Storage–60+100°C
ABSOLUTE MAXIMUM RATINGS*
MinMaxUnits
V
DD
to GND–0.37.0V
DC Input Voltage–0.3V
DD
+ 0.3V
Latch-Up Trigger Current–1000+1000mA
Soldering+300°C
10sec
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.