Analog Devices AD5341BRU, AD5341, AD5331BRU, AD5331, AD5330BRU Datasheet

a 2.5 V to 5.5 V, 115 A, Parallel Interface

Single Voltage-Output 8-/10-/12-Bit DACs

AD5330/AD5331/AD5340/AD5341*

FEATURES

AD5330: Single 8-Bit DAC in 20-Lead TSSOP AD5331: Single 10-Bit DAC in 20-Lead TSSOP AD5340: Single 12-Bit DAC in 24-Lead TSSOP AD5341: Single 12-Bit DAC in 20-Lead TSSOP

Low Power Operation: 115 A @ 3 V, 140 A @ 5 V

Power-Down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin 2.5 V to 5.5 V Power Supply

Double-Buffered Input Logic

Guaranteed Monotonic by Design Over All Codes Buffered/Unbuffered Reference Input Options

Output Range: 0–VREF or 0–2 VREF Power-On Reset to Zero Volts

Simultaneous Update of DAC Outputs via LDAC Pin Asynchronous CLR Facility

Low Power Parallel Data Interface

On-Chip Rail-to-Rail Output Buffer Amplifiers Temperature Range: –40 C to +105 C

APPLICATIONS

Portable Battery-Powered Instruments

Digital Gain and Offset Adjustment

Programmable Voltage and Current Sources

Programmable Attenuators

Industrial Process Control

GENERAL DESCRIPTION

The AD5330/AD5331/AD5340/AD5341 are single 8-, 10-, and 12-bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 115 µA at 3 V, and feature a power-down mode that further reduces the current to 80 nA. These devices incorporate an on-chip output buffer that can drive the output to both supply rails, while the AD5330, AD5340, and AD5341 allow a choice of buffered or unbuffered reference input.

The AD5330/AD5331/AD5340/AD5341 have a parallel interface. CS selects the device and data is loaded into the input registers on the rising edge of WR.

The GAIN pin allows the output range to be set at 0 V to VREF or 0 V to 2 × VREF.

Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the LDAC pin.

An asynchronous CLR input is also provided, which resets the contents of the Input Register and the DAC Register to all zeros. These devices also incorporate a power-on reset circuit that ensures that the DAC output powers on to 0 V and remains there until valid data is written to the device.

The AD5330/AD5331/AD5340/AD5341 are available in Thin Shrink Small Outline Packages (TSSOP).

AD5330 FUNCTIONAL BLOCK DIAGRAM

(Other Diagrams Inside)

			VREF	VDD
	POWER-ON			AD5330
	RESET
BUF
GAIN	INPUT	DAC
DB	REGISTER	REGISTER	8-BIT	BUFFER	V
						OUT
. 7	INTER-		DAC
.
DB0	FACE
	LOGIC
CS
WR
CLR	RESET			POWER-DOWN
				LOGIC
LDAC
				PD	GND

*Protected by U.S. Patent Number 5,969,657; other patents pending.

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: [phone]	World Wide Web Site: http://www.analog.com
Fax: [phone]	© Analog Devices, Inc., 2000

AD5330/AD5331/AD5340/AD5341–SPECIFICATIONS

(VDD = 2.5 V to 5.5 V, VREF = 2 V. RL = 2 k to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless otherwise noted.)

Parameter1		B Version2
	Min	Typ	Max	Unit	Conditions/Comments
DC PERFORMANCE3, 4
AD5330
Resolution		8		Bits
Relative Accuracy		±0.15	±1	LSB
Differential Nonlinearity		±0.02	±0.25	LSB	Guaranteed Monotonic By Design Over All Codes
AD5331
Resolution		10		Bits
Relative Accuracy		±0.5	±4	LSB
Differential Nonlinearity		±0.05	±0.5	LSB	Guaranteed Monotonic By Design Over All Codes
AD5340/AD5341
Resolution		12		Bits
Relative Accuracy		±2	±16	LSB
Differential Nonlinearity		±0.2	±1	LSB	Guaranteed Monotonic By Design Over All Codes
Offset Error		±0.4	±3	% of FSR
Gain Error		±0.15	±1	% of FSR
Lower Deadband5		10	60	mV	Lower Deadband Exists Only if Offset Error Is Negative
Upper Deadband		10	60	mV	VDD = 5 V. Upper Deadband Exists Only if VREF = VDD
Offset Error Drift6		–12		ppm of FSR/°C
Gain Error Drift6		–5		ppm of FSR/°C	∆VDD = ±10%
DC Power Supply Rejection Ratio6		–60		dB
DAC REFERENCE INPUT6
VREF Input Range	1		VDD	V	Buffered Reference (AD5330, AD5340, and AD5341)
	0.25		VDD	V	Unbuffered Reference
VREF Input Impedance		>10		MΩ	Buffered Reference (AD5330, AD5340, and AD5341)
		180		kΩ	Unbuffered Reference. Gain = 1, Input Impedance = RDAC
		90		kΩ	Unbuffered Reference. Gain = 2, Input Impedance = RDAC
Reference Feedthrough		–90		dB	Frequency = 10 kHz
OUTPUT CHARACTERISTICS6
Minimum Output Voltage4, 7		0.001		V min	Rail-to-Rail Operation
Maximum Output Voltage4, 7		VDD–0.001		V max
DC Output Impedance		0.5		Ω
Short Circuit Current		25		mA	VDD = 5 V
		15		mA	VDD = 3 V
Power-Up Time		2.5		µs	Coming Out of Power-Down Mode. VDD = 5 V
		5		µs	Coming Out of Power-Down Mode. VDD = 3 V
LOGIC INPUTS6		±1		µA
Input Current					VDD = 5 V ± 10%
VIL, Input Low Voltage			0.8	V
			0.6	V	VDD = 3 V ± 10%
			0.5	V	VDD = 2.5 V
VIH, Input High Voltage	2.4			V	VDD = 5 V ± 10%
	2.1			V	VDD = 3 V ± 10%
	2.0			V	VDD = 2.5 V
Pin Capacitance		3		pF
POWER REQUIREMENTS
VDD	2.5		5.5	V
IDD (Normal Mode)				µA	DACs active and excluding load currents. Unbuffered
VDD = 4.5 V to 5.5 V		140	250		Reference. VIH = VDD, VIL = GND.
VDD = 2.5 V to 3.6 V		115	200	µA	IDD increases by 50 µA at VREF > VDD – 100 mV.
					In Buffered Mode extra current is (5 + VREF/RDAC) µA,
IDD (Power-Down Mode)					where RDAC is the resistance of the resistor string.
				µA
VDD = 4.5 V to 5.5 V		0.2	1
VDD = 2.5 V to 3.6 V		0.08	1	µA

NOTES

1See Terminology section.

2Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.

3Linearity is tested using a reduced code range: AD5330 (Code 8 to 255); AD5331 (Code 28 to 1023); AD5340/AD5341 (Code 115 to 4095). 4DC specifications tested with output unloaded.

5This corresponds to x codes. x = Deadband voltage/LSB size. 6Guaranteed by design and characterization, not production tested.

7In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, VREF = VDD and “Offset plus Gain” Error must be positive.

Specifications subject to change without notice.

–2–

REV. 0

						AD5330/AD5331/AD5340/AD5341
1 (VDD = 2.5 V to 5.5 V. RL = 2 k to GND; CL = 200 pF to GND; all specifications TMIN to TMAX
AC CHARACTERISTICS	unless otherwise noted.)
Parameter2			B Version3
		Min	Typ	Max	Unit		Conditions/Comments
Output Voltage Settling Time					s		VREF = 2 V. See Figure 20
AD5330			6	8			1/4 Scale to 3/4 Scale Change (40 H to C0 H)
AD5331			7	9	s		1/4 Scale to 3/4 Scale Change (100 H to 300 H)
AD5340			8	10	s		1/4 Scale to 3/4 Scale Change (400 H to C00 H)
AD5341			8	10	s		1/4 Scale to 3/4 Scale Change (400 H to C00 H)
Slew Rate			0.7		V/ s
Major Code Transition Glitch Energy			6		nV-s		1 LSB Change Around Major Carry
Digital Feedthrough			0.5		nV-s		VREF = 2 V ± 0.1 V p-p. Unbuffered Mode
Multiplying Bandwidth			200		kHz
Total Harmonic Distortion			–70		dB		VREF = 2.5 V ± 0.1 V p-p. Frequency = 10 kHz

NOTES

1Guaranteed by design and characterization, not production tested.

2See Terminology section.

3Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.

Specifications subject to change without notice.

TIMING CHARACTERISTICS1, 2, 3 (VDD = 2.5 V to 5.5 V, All specifications TMIN to TMAX unless otherwise noted.)

Parameter	Limit at TMIN, TMAX	Unit	Condition/Comments
t1	0	ns min	CS to WR Setup Time
t2	0	ns min	CS to WR Hold Time
t3	20	ns min	WR Pulsewidth
t4	5	ns min	Data, GAIN, BUF, HBEN Setup Time
t5	4.5	ns min	Data, GAIN, BUF, HBEN Hold Time
t6	5	ns min	Synchronous Mode. WR Falling to LDAC Falling.
t7	5	ns min	Synchronous Mode. LDAC Falling to WR Rising.
t8	4.5	ns min	Synchronous Mode. WR Rising to LDAC Rising.
t9	5	ns min	Asynchronous Mode. LDAC Rising to WR Rising.
t10	4.5	ns min	Asynchronous Mode. WR Rising to LDAC Falling.
t11	20	ns min	LDAC Pulsewidth
t12	20	ns min	CLR Pulsewidth
t13	50	ns min	Time Between WR Cycles

NOTES

1Guaranteed by design and characterization, not production tested.

2All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3See Figure 1.

t1				t2

CS

t3 t13

WR

t5

DATA,

t4

GAIN,

BUF,

HBEN

t8

t6

t7

LDAC1

t9 t10 t11

LDAC2

t12

CLR

NOTES:

1SYNCHRONOUS LDAC UPDATE MODE

2ASYNCHRONOUS LDAC UPDATE MODE

Figure 1. Parallel Interface Timing Diagram

REV. 0

–3–

AD5330/AD5331/AD5340/AD5341

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C unless otherwise noted)

VDD to GND . . . . . . . . . . . . . . .	. . . . . . . . . .	. –0.3 V to +7 V
Digital Input Voltage to GND . .	. . . . . –0.3 V to VDD + 0.3		V
Digital Output Voltage to GND	. . . . . –0.3 V to VDD + 0.3		V
Reference Input Voltage to GND	. . . . –0.3 V to VDD + 0.3		V
VOUT to GND . . . . . . . . . . . . . .	. . . . . –0.3 V to VDD + 0.3		V
Operating Temperature Range		–40°C to +105°C
Industrial (B Version) . . . . . .	. . . . . . . . .
Storage Temperature Range . . .	. . . . . . . . .	–65°C to +150°C
Junction Temperature . . . . . . . .	. . . . . . . . . .	. . . . . . . 150°C
TSSOP Package	(TJ max – TA)/θJA mW
Power Dissipation . . . . . . . . . .
θJA Thermal Impedance (20-Lead TSSOP)		. . . . . 143°C/W
θJA Thermal Impedance (24-Lead TSSOP)		. . . . . 128°C/W
θJA Thermal Impedance (20-Lead TSSOP)		. . . . . . 45°C/W
θJC Thermal Impedance (24-Lead TSSOP)		. . . . . . 42°C/W

Reflow Soldering	220 +5/–0°C
Peak Temperature . . . . . . . . . . . . . . . . . . . .
Time at Peak Temperature . . . . . . . . . . . .	10 sec to 40 sec

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING GUIDE

			Package
Model	Temperature Range	Package Description	Option
AD5330BRU	–40°C to +105°C	TSSOP (Thin Shrink Small Outline Package)	RU-20
AD5331BRU	–40°C to +105°C	TSSOP (Thin Shrink Small Outline Package)	RU-20
AD5340BRU	–40°C to +105°C	TSSOP (Thin Shrink Small Outline Package)	RU-24
AD5341BRU	–40°C to +105°C	TSSOP (Thin Shrink Small Outline Package)	RU-20

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5330/AD5331/AD5340/AD5341 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. 0

AD5330/AD5331/AD5340/AD5341

AD5330 FUNCTIONAL BLOCK DIAGRAM

AD5330 PIN CONFIGURATION

			VREF	VDD
	POWER-ON			AD5330
	RESET
BUF
GAIN	INPUT	DAC
DB	REGISTER	REGISTER	8-BIT	BUFFER	VOUT
. 7	INTER-		DAC
.
DB0	FACE
	LOGIC
CS
WR
CLR	RESET			POWER-DOWN
				LOGIC
LDAC
				PD	GND

					DB7
	BUF	1		20
					DB6
	NC	2		19
	VREF				DB5
		3		18
	VOUT				DB4
		4	8-BIT	17
	GND				DB3
		5	AD5330	16
	CS		TOP VIEW		DB2
		6		15
			(Not to Scale)
					DB1
	WR	7		14
	GAIN				DB0
		8		13
					VDD
	CLR	9		12
					PD
	LDAC	10		11

NC = NO CONNECT

		AD5330 PIN FUNCTION DESCRIPTIONS
Pin
No.	Mnemonic	Function
1	BUF	Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
2	NC	No Connect.
3	VREF	Reference Input.
4	VOUT	Output of DAC. Buffered output with rail-to-rail operation.
5	GND	Ground reference point for all circuitry on the part.
6	CS	Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
7	WR	Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
8	GAIN	Gain Control Pin. This controls whether the output range from the DAC is 0–VREF or 0–2 VREF.
9	CLR	Asynchronous active low control input that clears all input registers and DAC registers to zero.
10	LDAC	Active low control input that updates the DAC registers with the contents of the input registers.
11	PD	Power-Down Pin. This active low control pin puts the DAC into power-down mode.
12	VDD	Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled
		with a 10 F capacitor in parallel with a 0.1 F capacitor to GND.
13–20	DB0–DB7	Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.

REV. 0

–5–

AD5330/AD5331/AD5340/AD5341

AD5331 FUNCTIONAL BLOCK DIAGRAM

AD5331 PIN CONFIGURATION

			VREF	VDD
						DB8	1		20	DB7
	POWER-ON			AD5331		DB9	2		19	DB6
	RESET					VREF	3		18	DB5
BUF						VOUT	4	10-BIT	17	DB4
	INPUT	DAC				GND	5		16	DB3
								AD5331
DB	REGISTER	REGISTER	10-BIT	BUFFER	VOUT	CS	6	TOP VIEW	15	DB
											2
. 9	INTER-		DAC					(Not to Scale)
.
DB0	FACE					WR 7			14	DB1
	LOGIC					GAIN	8		13	DB0
CS
WR						CLR	9		12	VDD
						LDAC 10			11	PD
	RESET			POWER-DOWN
CLR
				LOGIC
LDAC
				PD	GND

		AD5331 PIN FUNCTION DESCRIPTIONS
Pin
No.	Mnemonic	Function
1	DB8	Parallel Data Input.
2	DB9	Most Significant Bit of Parallel Data Input.
3	VREF	Unbuffered Reference Input.
4	VOUT	Output of DAC. Buffered output with rail-to-rail operation.
5	GND	Ground reference point for all circuitry on the part.
6	CS	Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
7	WR	Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
8	GAIN	Gain Control Pin. This controls whether the output range from the DAC is 0–VREF or 0–2 VREF.
9	CLR	Active low control input that clears all input registers and DAC registers to zero.
10	LDAC	Active low control input that updates the DAC registers with the contents of the input registers.
11	PD	Power-Down Pin. This active low control pin puts the DAC into power-down mode.
12	VDD	Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled
		with a 10 F capacitor in parallel with a 0.1 F capacitor to GND.
13–20	DB0–DB7	Eight Parallel Data Inputs.

–6–

REV. 0