Analog Devices AD566ATD, AD566ASD, AD566AKD, AD566AJD, AD566A Datasheet

a		High Speed 12-Bit
		Monolithic D/A Converters
		AD565A*/AD566A*

FEATURES

Single Chip Construction

Very High-Speed Settling to 1/2 LSB AD565A: 250 ns max

AD566A: 350 ns max Full-Scale Switching Time: 30 ns

Guaranteed for Operation with 12 V Supplies:

AD565A with –12 V Supply: AD566A Linearity Guaranteed Over Temperature:

1/2 LSB max (K, T Grades)

Monotonicity Guaranteed Over Temperature Low Power: AD566A = 180 mW max;

AD565A = 225 mW max

Use with On-Board High-Stability Reference (AD565A) or with External Reference (AD566A)

Low Cost

MlL-STD-883-Compliant Versions Available

PRODUCT DESCRIPTION

The AD565A and AD566A are fast 12-bit digital-to-analog converters that incorporate the latest advances in analog circuit design to achieve high speeds at low cost.

The AD565A and AD566A use 12 precision, high-speed bipolar current-steering switches, control amplifier and a laser-trimmed thin-film resistor network to produce a very fast, high accuracy analog output current. The AD565A also includes a buried Zener reference that features low-noise, long-term stability and temperature drift characteristics comparable to the best discrete reference diodes.

The combination of performance and flexibility in the AD565A and AD566A has resulted from major innovations in circuit design, an important new high-speed bipolar process, and continuing advances in laser-wafer-trimming techniques (LWT). The AD565A and AD566A have a 10–90% full-scale transition time less than 35 ns and settle to within ±1/2 LSB in 250 ns max (350 ns for AD566A). Both are laser-trimmed at the wafer level to ±1/8 LSB typical linearity and are specified to ±1/4 LSB max error (K and T grades) at +25°C. High speed and accuracy make the AD565A and AD566A the ideal choice for high-speed display drivers as well as fast analog-to-digital converters.

The laser trimming process which provides the excellent linearity is also used to trim both the absolute value and the temperature coefficient of the reference of the AD565A resulting in a typical full-scale gain TC of 10 ppm/°C. When tighter TC performance is required or when a system reference is available, the AD566A may be used with an external reference.

*Covered by Patent Nos.: 3,803,590; RE 28,633; 4,213,806; 4,136,349; 4,020,486; 3,747,088.

REV. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAMS

	REF OUT	VCC		BIPOLAR OFF
					20V SPAN
	10V		AD565A		5k
REF	19.95k		0.5mA	9.95k	10V SPAN
IN			IREF		5k
				DAC	DAC OUT
	20k		IOUT =
REF				IO	8k
GND			4 IREF CODE
			CODE INPUT
	–VEE		POWER MSB	LSB
			GND	BIPOLAR OFF

		AD566A		20V SPAN
				5k
			9.95k
REF	19.95k	0.5mA		10V SPAN
				5k
IN		IREF
			DAC	DAC OUT
	20k	IOUT =
REF			IO	8k
GND		4 IREF CODE
		CODE INPUT
	–VEE	POWER MSB	LSB
		GND

AD565A and AD566A are available in four performance grades. The J and K are specified for use over the 0°C to +70°C temperature range while the S and T grades are specified for the –55°C to +125°C range. The D grades are all packaged in a 24-lead, hermetically sealed, ceramic, dual-in-line package. The JR grade is packaged in a 28-lead plastic SOIC.

PRODUCT HIGHLIGHTS

1.The wide output compliance range of the AD565A and AD566A are ideally suited for fast, low noise, accurate voltage output configurations without an output amplifier.

2.The devices incorporate a newly developed, fully differential, nonsaturating precision current switching cell structure which combines the dc accuracy and stability first developed in the AD562/3 with very fast switching times and an optimally-damped settling characteristic.

3.The devices also contain SiCr thin film application resistors which can be used with an external op amp to provide a precision voltage output or as input resistors for a successive approximation A/D converter. The resistors are matched to the internal ladder network to guarantee a low gain temperature coefficient and are laser-trimmed for minimum full-scale and bipolar offset errors.

4.The AD565A and AD566A are available in versions compliant with MIL-STD-883. Refer to the Analog Devices Military Products Databook or current /883B data sheet for detailed specifications.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: [phone]	World Wide Web Site: http://www.analog.com
Fax: [phone]	© Analog Devices, Inc., 2000

AD565A–SPECIFICATIONS (TA = +25 C, VCC = +15 V, VEE = +15 V, unless otherwise noted.)

		AD565AJ			AD565AK
Model	Min	Typ	Max	Min	Typ	Max	Units
DATA INPUTS1 (Pins 13 to 24)
TTL or 5 Volt CMOS
Input Voltage	+2.0		+5.5	+2.0		+5.5
Bit ON Logic “1”							V
Bit OFF Logic “0”			+0.8			+0.8	V
Logic Current (Each Bit)			+300			+300	µA
Bit ON Logic “1”		+120			+120
Bit OFF Logic “0”		+35	+100		+35	+100	µA
RESOLUTION			12			12	Bits
OUTPUT
Current	–1.6		–2.4	–1.6		–2.4
Unipolar (All Bits On)		–2.0			–2.0		mA
Bipolar (All Bits On or Off)	0.8	±1.0	1.2	0.8	±1.0	1.2	mA
Resistance (Exclusive of Span Resistors)	6	8	10	6	8	10	kΩ
Offset			0.05			0.05
Unipolar		0.01			0.01		% of F.S. Range
Bipolar (Figure 3, R2 = 50 Ω Fixed)		0.05	0.15		0.05	0.1	% of F.S. Range
Capacitance		25			25		pF
Compliance Voltage
TMIN to TMAX	–1.5		+10	–1.5		+10	V
ACCURACY (Error Relative to		±1/4			±1/8
Full Scale) +25°C			1/2			1/4	LSB
		(0.006)	(0.012)		(0.003)	(0.006)	% of F.S. Range
TMIN to TMAX		±1/2	3/4		±1/4	1/2	LSB
		(0.012)	(0.018)		(0.006)	(0.012)	% of F.S. Range
DIFFERENTIAL NONLINEARITY		±1/2			±1/4
+25°C			3/4			1/2	LSB
TMIN to TMAX	MONOTONICITY GUARANTEED			MONOTONICITY GUARANTEED
TEMPERATURE COEFFICIENTS
With Internal Reference			2			2	ppm/°C
Unipolar Zero		1			1
Bipolar Zero		5	10		5	10	ppm/°C
Gain (Full Scale)		15	50		10	20	ppm/°C
Differential Nonlinearity		2			2		ppm/°C
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON		250	400		250	400	ns
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time		15	30		15	30	ns
90% to 10% Delay plus Fall Time		30	50		30	50	ns
TEMPERATURE RANGE							°C
Operating	0		+70	0		+70
Storage	–65		+150	–65		+150	°C
POWER REQUIREMENTS			5			5
VCC, +11.4 to +16.5 V de		3			3		mA
VEE, –11.4 to –16.5 V dc		–12	–18		–12	–18	mA
POWER SUPPLY GAIN SENSITIVITY2			10			10
VCC = +11.4 to +16.5 V dc		3			3		ppm of F.S./%
VEE = –11.4 to –16.5 V dc		15	25		15	25	ppm of F.S./%
PROGRAMMABLE OUTPUT RANGES
(See Figures 2, 3, 4)		0 to +5			0 to +5		V
		–2.5 to +2.5			–2.5 to +2.5		V
		0 to +10			0 to +10		V
		–5 to +5			–5 to +5		V
		–10 to +10			–10 to +10		V
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω		±0.1	0.25		±0.1	0.25
Resistor for R2 (Figure 2)							% of F.S. Range
Bipolar Zero Error with Fixed		±0.05			±0.05	±0.1
50 Ω Resistor for R1 (Figure 3)	±0.25		0.15	±0.25			% of F.S. Range
Gain Adjustment Range (Figure 2)							% of F.S. Range
Bipolar Zero Adjustment Range	±0.15			±0.15			% of F.S. Range
REFERENCE INPUT							kΩ
Input Impedance	15	20	25	15	20	25
REFERENCE OUTPUT	9.90		10.10	9.90		10.10
Voltage		10.00			10.00		V
Current (Available for External Loads)3	1.5	2.5		1.5	2.5		mA
POWER DISSIPATION		225	345		225	345	mW

NOTES

1The digital inputs are guaranteed but not tested over the operating temperature range. 2The power supply gain sensitivity is tested in reference to a VCC, VEE of ±15 V dc.

3For operation at elevated temperatures the reference cannot supply current for external loads. It, therefore, should be buffered if additional loads are to be supplied.

Specifications subject to change without notice.

–2–

REV. D

						AD565A/AD566A
		AD565AS			AD565AT
Model	Min	Typ	Max	Min	Typ	Max	Units
DATA INPUTS1 (Pins 13 to 24)
TTL or 5 Volt CMOS
Input Voltage	+2.0		+5.5	+2.0		+5.5
Bit ON Logic “1”							V
Bit OFF Logic “0”			+0.8			+0.8	V
Logic Current (Each Bit)			+300			+300	µA
Bit ON Logic “1”		+120			+120
Bit OFF Logic “0”		+35	+100		+35	+100	µA
RESOLUTION			12			12	Bits
OUTPUT
Current	–1.6		–2.4	–1.6		–2.4
Unipolar (All Bits On)		–2.0			–2.0		mA
Bipolar (All Bits On or Off)	0.8	±1.0	1.2	0.8	±1.0	1.2	mA
Resistance (Exclusive of Span Resistors)	6	8	10	6	8	10	kΩ
Offset			0.05			0.05
Unipolar		0.01			0.01		% of F.S. Range
Bipolar (Figure 3, R2 = 50 Ω Fixed)		0.05	0.15		0.05	0.1	% of F.S. Range
Capacitance		25			25		pF
Compliance Voltage
TMIN to TMAX	–1.5		+10	–1.5		+10	V
ACCURACY (Error Relative to
Full Scale) +25°C		±1/4	1/2		±1/8	1/4	LSB
		(0.006)	(0.012)		(0.003)	(0.006)	% of F.S. Range
TMIN to TMAX		±1/2	3/4		±1/4	1/2	LSB
		(0.012)	(0.018)		(0.006)	(0.012)	% of F.S. Range
DIFFERENTIAL NONLINEARITY		±1/2			±1/4
+25°C			3/4			1/2	LSB
TMIN to TMAX	MONOTONICITY GUARANTEED			MONOTONICITY GUARANTEED
TEMPERATURE COEFFICIENTS
With Internal Reference			2			2	ppm/°C
Unipolar Zero		1			1
Bipolar Zero		5	10		5	10	ppm/°C
Gain (Full Scale)		15	30		10	15	ppm/°C
Differential Nonlinearity		2			2		ppm/°C
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON		250	400		250	400	ns
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time		15	30		15	30	ns
90% to 10% Delay plus Fall Time		30	50		30	50	ns
TEMPERATURE RANGE							°C
Operating	–55		+125	–55		+125
Storage	–65		+150	–65		+150	°C
POWER REQUIREMENTS			5			5
VCC, +11.4 to +16.5 V dc		3			3		mA
VEE, –11.4 to –16.5 V dc		–12	–18		–12	–18	mA
POWER SUPPLY GAIN SENSITIVITY2			10			10
VCC = +11.4 to +16.5 V dc		3			3		ppm of F.S./%
VEE = –11.4 to –16.5 V dc		15	25		15	25	ppm of F.S./%
PROGRAMMABLE OUTPUT RANGES
(See Figures 2, 3, 4)		0 to +5			0 to +5		V
		–2.5 to +2.5			–2.5 to +2.5		V
		0 to +10			0 to +10		V
		–5 to +5			–5 to +5		V
		–10 to +10			–10 to +10		V
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω		±0.1	0.25		±0.1	0.25
Resistor for R2 (Figure 2)							% of F.S. Range
Bipolar Zero Error with Fixed		±0.05			±0.05
50 Ω Resistor for R1 (Figure 3)	±0.25		0.15	±0.25		0.1	% of F.S. Range
Gain Adjustment Range (Figure 2)							% of F.S. Range
Bipolar Zero Adjustment Range	±0.15			±0.15			% of F.S. Range
REFERENCE INPUT							kΩ
Input Impedance	15	20	25	15	20	25
REFERENCE OUTPUT	9.90			9.90		10.10
Voltage		10.00	10.10		10.00		V
Current (Available for External Loads)3	1.5	2.5		1.5	2.5		mA
POWER DISSIPATION		225	345		225	345	mW

Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.

Specification subject to change without notice.

REV. D

–3–

AD566A–SPECIFICATIONS(TA = +25 C, VEE = –15 V, unless otherwise noted)

		AD566AJ			AD566AK
Model	Min	Typ	Max	Min	Typ	Max	Units
DATA INPUTS1 (Pins 13 to 24)
TTL or 5 Volt CMOS
Input Voltage	+2.0		+5.5	+2.0		+5.5
Bit ON Logic “1”							V
Bit OFF Logic “0”	0		+0.8	0		+0.8	V
Logic Current (Each Bit)			+300			+300	µA
Bit ON Logic “1”		+120			+120
Bit OFF Logic “0”		+35	+100		+35	+100	µA
RESOLUTION			12			12	Bits
OUTPUT
Current	–1.6		–2.4	–1.6		–2.4
Unipolar (All Bits On)		–2.0			–2.0		mA
Bipolar (All Bits On or Off)	0.8	± 1.0	1.2	0.8	± 1.0	1.2	mA
Resistance (Exclusive of Span Resistors)	6	8	10	6	8	10	kΩ
Offset			0.05			0.05
Unipolar (Adjustable to Zero per Figure 3)		0.01			0.01		% of F.S. Range
Bipolar (Figure 4, R1 and R2 = 50 Ω Fixed)		0.05	0.15		0.05	0.1	% of F.S. Range
Capacitance		25			25		pF
Compliance Voltage
TMIN to TMAX	–1.5		+10	–1.5		+10	V
ACCURACY (Error Relative to
Full Scale) +25°C		± 1/4	1/2		± 1/8	1/4	LSB
		(0.006)	(0.012)		(0.003)	(0.006)	% of F.S. Range
TMIN to TMAX		± 1/2	3/4		± 1/4	1/2	LSB
		(0.012)	(0.018)		(0.006)	(0.012)	% of F.S. Range
DIFFERENTIAL NONLINEARITY
+25°C		± 1/2	3/4		± 1/4	1/2	LSB
TMIN to TMAX	MONOTONICITY GUARANTEED			MONOTONICITY GUARANTEED
TEMPERATURE COEFFICIENTS			2			2	ppm/°C
Unipolar Zero		1			1
Bipolar Zero		5	10		5	10	ppm/°C
Gain (Full Scale)		7	10		3	5	ppm/°C
Differential Nonlinearity		2			2		ppm/°C
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON (Figure 8)		250	350		250	350	ns
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time		15	30		15	30	ns
90% to 10% Delay plus Fall Time		30	50		30	50	ns
POWER REQUIREMENTS			–18			–18
VEE, –11.4 to –16.5 V dc		–12			–12		mA
POWER SUPPLY GAIN SENSITIVITY2			25			25
VEE = –11.4 to –16.5 V dc		15			15		ppm of F.S./%
PROGRAMMABLE OUTPUT RANGES
(see Figures 3, 4, 5)		0 to +5			0 to +5		V
		–2.5 to +2.5			–2.5 to +2.5		V
		0 to +10			0 to +10		V
		–5 to +5			–5 to +5		V
		–10 to +10			–10 to +10		V
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω		± 0.1	0.25		± 0.1	0.25
Resistor for R2 (Figure 3)							% of F.S. Range
Bipolar Zero Error with Fixed
50 Ω Resistor for R1 (Figure 4)	± 0.25	± 0.05	0.15	± 0.25	± 0.05	0.1	% of F.S. Range
Gain Adjustment Range (Figure 3)							% of F.S. Range
Bipolar Zero Adjustment Range	± 0.15			± 0.15			% of F.S. Range
REFERENCE INPUT							kΩ
Input Impedance	15	20	25	15	20	25
POWER DISSIPATION		180	300		180	300	mW
MULTIPLYING MODE PERFORMANCE (All Models)
Quadrants		Two (2): Bipolar Operation at Digital Input Only
Reference Voltage		+1 V to +10 V, Unipolar
Accuracy		10 Bits (±0.05% of Reduced F.S.) for 1 V dc Reference Voltage
Reference Feedthrough (Unipolar Mode,
All Bits OFF, and 1 V to +10 V [p-p], Sine Wave
Frequency for 1/2 LSB [p-p] Feedthrough)		40 kHz typ
Output Slew Rate 10%–90%		5 mA/µs
90%–10%		1 mA/µs
Output Settling Time (All Bits ON and a 0 V–10 V		1.5 µs to 0.01% F.S.
Step Change in Reference Voltage)
CONTROL AMPLIFIER
Full Power Bandwidth		300 kHz
Small-Signal Closed-Loop Bandwidth		1.8 MHz

NOTES

1The digital input levels are guaranteed but not tested over the temperature range. 2The power supply gain sensitivity is tested in reference to a VEE of –1.5 V dc.

Specifications subject to change without notice.

–4–

REV. D