Analog Devices AD5282BRU50, AD5282BRU200, AD5280BRU50, AD5280BRU200, AD5280BRU20 Datasheet

PRELIMINARY TECHNICAL DATA

a	+15V, I2C Compatible
	Digital Potentiometers
Preliminary Technical Data	AD5280/AD5282

FEATURES

256 Position AD5280 – 1-Channel

AD5282 – 2-Channel (Independently Programmable) Potentiometer Replacement

20K, 50K, 200K Ohm with TC < 50ppm/ºC Internal Power ON Mid-Scale Preset

+5 to +15V Single-Supply; ±5.5V Dual-Supply Operation I2C Compatible Interface

APPLICATIONS

Multi-Media, Video & Audio

Communications

Mechanical Potentiometer Replacement

Instrumentation: Gain, Offset Adjustment

Programmable Voltage to Current Conversion

Line Impedance Matching

GENERAL DESCRIPTION

The AD5280/AD5282 provides a single/dual channel, 256 position digitally-controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as a potentiometer, trimmer or variable resistor. Each VR offers a completely programmable value of resistance, between the A terminal and the wiper, or the B terminal and the wiper. The fixed A-to-B terminal resistance of 20, 50 or 200K ohms has a 1% channel-to-channel matching tolerance with a nominal temperature coefficient of 30 ppm/°C.

Wiper Position programming defaults to midscale at system power ON. Once powered the VR wiper position is programmed by a I2C compatible 2-wire serial data interface. Both parts have two programmable logic outputs available to drive digital loads, gates, LED drivers, analog switches, etc.

FUNCTIONAL BLOCK DIAGRAMS

A1

W1

B1

O1

O2

SHDN

VDD

VSS	RDAC1 REGISTER	RDAC2 REGISTER
	R	R
VL	ADDRESS
		PWR ON
	DECODE
	AD5280	RESET
		8

A1	W1	B1	A2	W2	B2	O1
SHDN						OUTPUT
						REGISTER

			R
	VDD	RDAC1 REGISTER	RDAC2 REGISTER
	VSS
		R	R
	VL	ADDRESS
			PWR ON
		DECODE
		AD5282	RESET
			8

SCL

SERIAL INPUT REGISTER

SDA

GND

AD0 AD1

The AD5280/AD5282 are available in ultra compact surface mount thin TSSOP-14/-16 packages. All parts are guaranteed to operate over the extended industrial temperature range of -40°C to +85°C. For 3-wire, SPI compatible interface applications, see AD5203/AD5204/AD5206/AD7376/AD8400/AD8402/AD8403/ AD5260/AD5262/AD5200/AD5201 products.

ORDERING GUIDE

	Kilo		Package	Package
Model	Ohms	Temp	Description	Option
AD5280BRU20	20	-40/+85°C	TSSOP-14	RU-14
AD5280BRU50	50	-40/+85°C	TSSOP-14	RU-14
AD5280BRU200	200	-40/+85°C	TSSOP-14	RU-14
AD5282BRU20	20	-40/+85°C	TSSOP-16	RU-16
AD5282BRU50	50	-40/+85°C	TSSOP-16	RU-16
AD5282BRU200	200	-40/+85°C	TSSOP-16	RU-16

The AD5280/AD5282 die size is 75 mil X 120 mil, 9,000 sq. mil. Contains xxx transistors. Patent Number xxx applies.

SCL

SERIAL INPUT REGISTER

SDA GND

AD0 AD1

REV PrE 12 MAR 02

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: [phone]	www.analog.com
Fax: [phone]	©Analog Devices, Inc., 2002

PRELIMINARY TECHNICAL DATA

AD5280/AD5282

ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION (VDD = +5V, VSS = -5V, VLOGIC = +5V,

VA = +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)

Min

Typ1

Max

Units

Parameter

Symbol

Conditions

DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs

Resistor Differential NL2

R-DNL

R

, V

A

=NC

-1

±0.4

+1

LSB

Resistor Nonlinearity2

WB

R-INL

R

, V

A

=NC

-1

±0.5

+1

LSB

WB

Nominal resistor tolerance3

∆ R

TA = 25°C

-30

30

%

Resistance Temperature Coefficient

RAB/∆ T

VAB = VDD, Wiper = No Connect

30

ppm/°C

Wiper Resistance

RW

IW = VDD /R, VDD = +3V or +5V

40

100

Ω

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE

Specifications apply to all VRs

Resolution

N

8

Bits

Integral Nonlinearity4

INL

RAB=20KΩ , 50KΩ

–1

±0.5

+1

LSB

Integral Nonlinearity4

INL

RAB=200KΩ

–2

±0.5

+2

LSB

Differential Nonlinearity4

DNL

–1

±0.4

+1

LSB

Voltage Divider Temperature Coefficient

∆ VW/∆ T

Code = 80H

5

ppm/°C

Full-Scale Error

VWFSE

Code = FFH

–1

-0.5

+0

LSB

Zero-Scale Error

VWZSE

Code = 00H

0

+0.5

+1

LSB

RESISTOR TERMINALS

Voltage Range5

V

VSS

V

DD

V

A,B,W

Capacitance6 A, B

CA,B

f = 1 MHz, measured to GND, Code = 80H

45

pF

Capacitance6 W

CW

f = 1 MHz, measured to GND, Code = 80H

60

pF

Common Mode Leakage

ICM

VA = VB = VW

1

nA

DIGITAL INPUTS

Input Logic High

VIH

SDA & SCL

0.7VLOGIC

VLOGIC+0.5

V

Input Logic Low

VIL

SDA & SCL

-0.5

0.3VLOGIC

V

Input Logic High

VIH

AD0 & AD1

2.4

VLOGIC

V

Input Logic Low

VIL

AD0 & AD1

0

0.8

V

Input Logic High

VIH

VLOGIC = +3V, AD0 & AD1

2.1

VLOGIC

V

Input Logic Low

VIL

VLOGIC = +3V, AD0 & AD1

0

0.6

V

Input Current

IIL

VIN = 0V or +5V

±1

µA

Input Capacitance6

C

3

pF

IL

DIGITAL Output

O1, O2

VOH

IOH=0.4mA

2.4

5.5

V

O1, O2

VOL

IOL=-1.6mA

0

0.4

V

SDA

VOL

IOL = -6mA

0.6

V

SDA

VOL

IOL = -3mA

0.4

V

Three-State Leakage Current

IOZ

VIN = 0V or +5V

±1

µA

Output Capacitance6

C

3

8

pF

OZ

POWER SUPPLIES

Logic Supply

VLOGIC

+2.7

+5.5

V

Power Single-Supply Range

VDD RANGE

VSS = 0V

+5

+15

V

Power Dual-Supply Range

VDD/SS RANGE

±4.5

±5.5

V

Logic Supply Current

ILOGIC

VLOGIC = +5V

10

µA

Positive Supply Current

IDD

VIH = +5V or VIL = 0V

20

60

µA

Negative Supply Current

ISS

20

60

µA

Power Dissipation10

P

V

IH

= +5V or V

IL

= 0V, V

= +5V, V

SS

= -5V

0.2

0.6

mW

DISS

DD

Power Supply Sensitivity

PSS

0.05

0.015

%/%

2	REV PrE 12 MAR 02

Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL [phone]; FAX [phone]; email; [e-mail]

PRELIMINARY TECHNICAL DATA

AD5280/AD5282

ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION (VDD = +5V, VSS = -5V, VLOGIC = +5V,

VA = +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)

Parameter		Symbol	Conditions	Min	Typ1	Max	Units
DYNAMIC CHARACTERISTICS6,9,11
Bandwidth –3dB		BW_20K	RAB = 20KΩ , Code = 80H		650		kHz
		BW_50K	RAB = 50KΩ , Code = 80H		142		kHz
		BW_200K	RAB = 200KΩ , Code = 80H		69		kHz
Total Harmonic Distortion		THDW	VA =1Vrms + 2V dc, VB = 2V DC, f=1KHz		0.005		%
VW Settling Time		tS	VA= VDD, VB=0V, ±1 LSB error band		2		µs
Resistor Noise Voltage		eN_WB	RWB = 10KΩ , f = 1KHz		14		nV√ Hz
INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12)
SCL Clock Frequency		fSCL		0		400	KHz
tBUF Bus free time between STOP & START		t1		1.3			µs
tHD;STA Hold Time (repeated START)		t2	After this period the first clock pulse is generated	0.6			µs
tLOW Low Period of SCL Clock		t3		1.3			µs
tHIGH High Period of SCL Clock		t4		0.6			µs
tSU;STA Setup Time For START Condition		t5		0.6			µs
tHD;DAT Data Hold Time		t6		0		0.9	µs
tSU;DAT Data Setup Time		t7		100			ns
tF Fall Time of both SDA & SCL signals		t8				300	ns
tR Rise Time of both SDA & SCL signals		t9				300	ns
tSU;STO Setup time for STOP Condition		t10		0.6			µs

NOTES:

1.Typicals represent average readings at +25°C, VDD = +5V, VSS = -5V.

2.Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3.VAB = VDD, Wiper (VW) = No connect

4.INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V. DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions.

5.Resistor terminals A,B,W have no limitations on polarity with respect to each other.

6.Guaranteed by design and not subject to production test.

9.Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value result in the minimum overall power consumption.

10.PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation.

11.All dynamic characteristics use VDD = +5V.

12.See timing diagram for location of measured values.

REV PrE 12 MAR 02

3

Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL [phone]; FAX [phone]; email; [e-mail]