Analog Devices AD5303, AD5323, AD5313 Datasheet

a		+2.5 V to +5.5 V, 230 A, Dual Rail-to-Rail
		Voltage Output 8-/10-/12-Bit DACs
		AD5303/AD5313/AD5323*

FEATURES

AD5303: Two Buffered 8-Bit DACs in One Package AD5313: Two Buffered 10-Bit DACs in One Package AD5323: Two Buffered 12-Bit DACs in One Package 16-Lead TSSOP Package

Micropower Operation: 300 A @ 5 V (Including

Reference Current)

Power-Down to 200 nA @ 5 V, 50 nA @ 3 V +2.5 V to +5.5 V Power Supply Double-Buffered Input Logic

Guaranteed Monotonic By Design Over All Codes Buffered/Unbuffered Reference Input Options Output Range: 0–VREF or 0–2 VREF Power-On-Reset to Zero Volts

SDO Daisy-Chaining Option

Simultaneous Update of DAC Outputs via LDAC Pin Asynchronous CLR Facility

Low Power Serial Interface with Schmitt-Triggered Inputs

On-Chip Rail-to-Rail Output Buffer Amplifiers

APPLICATIONS

Portable Battery Powered Instruments

Digital Gain and Offset Adjustment

Programmable Voltage and Current Sources

Programmable Attenuators

GENERAL DESCRIPTION

The AD5303/AD5313/AD5323 are dual 8-, 10and 12-bit buffered voltage output DACs in a 16-lead TSSOP package that operate from a single +2.5 V to +5.5 V supply consuming 230 A at 3 V. Their on-chip output amplifiers allow the outputs to swing rail-to-rail with a slew rate of 0.7 V/ s. The AD5303/ AD5313/AD5323 utilize a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI™, QSPI, MICROWIRE™ and DSP interface standards.

The references for the two DACs are derived from two reference pins (one per DAC). These reference inputs may be configured as buffered or unbuffered inputs. The parts incorporate a power- on-reset circuit that ensures that the DAC outputs power-up to 0 V and remain there until a valid write to the device takes place. There is also an asynchronous active low CLR pin that clears both DACs to 0 V. The outputs of both DACs may be updated simultaneously using the asynchronous LDAC input. The parts contain a power-down feature that reduces the current consumption of the devices to 200 nA at 5 V (50 nA at 3 V) and provides software-selectable output loads while in power-down mode. The parts may also be used in daisy-chaining applications using the SDO pin.

The low power consumption of these parts in normal operation make them ideally suited to portable battery operated equipment. The power consumption is 1.5 mW at 5 V, 0.7 mW at

3 V, reducing to 1 W in power-down mode.

FUNCTIONAL BLOCK DIAGRAM

			VDD	BUF A	VREFA
POWER-ON						AD5303/AD5313/AD5323
	RESET
		INPUT		DAC	STRING	BUFFER	VOUTA
		REGISTER	REGISTER		DAC
SYNC	INTERFACE
	LOGIC				POWER-DOWN		RESISTOR
SCLK	>
					LOGIC		NETWORK
DIN
		INPUT		DAC	STRING	BUFFER	VOUTB
		REGISTER	REGISTER		DAC
SDO						GAIN-SELECT	RESISTOR
						LOGIC	NETWORK
DCEN	LDAC CLR	PD		BUF B	VREFB	GND

*Protected by U.S. Patent No. 5684481; other patents pending. SPI is a trademark of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corporation.

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Fax: [phone]	© Analog Devices, Inc., 1999

AD5303/AD5313/AD5323–SPECIFICATIONS

(VDD = +2.5 V to +5.5 V; VREF = +2 V; RL = 2 k to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless otherwise noted.)

Parameter1		B Version2
	Min	Typ	Max	Units	Conditions/Comments
DC PERFORMANCE3, 4
AD5303
Resolution		8		Bits
Relative Accuracy		± 0.15	± 1	LSB
Differential Nonlinearity		± 0.02	± 0.25	LSB	Guaranteed Monotonic by Design Over All Codes
AD5313
Resolution		10		Bits
Relative Accuracy		± 0.5	± 3	LSB
Differential Nonlinearity		± 0.05	± 0.5	LSB	Guaranteed Monotonic by Design Over All Codes
AD5323
Resolution		12		Bits
Relative Accuracy		± 2	± 12	LSB
Differential Nonlinearity		± 0.2	± 1	LSB	Guaranteed Monotonic by Design Over All Codes
Offset Error		± 0.4	± 3	% of FSR	See Figures 3 and 4
Gain Error		± 0.15	± 1	% of FSR	See Figures 3 and 4
Lower Deadband		10	60	mV	See Figures 3 and 4
Offset Error Drift5		–12		ppm of FSR/°C
Gain Error Drift5		–5		ppm of FSR/°C	∆VDD = ± 10%
Power Supply Rejection Ratio5		–60		dB
DC Crosstalk5		30		µV
DAC REFERENCE INPUTS5
VREF Input Range	1		VDD	V	Buffered Reference Mode
	0		VDD	V	Unbuffered Reference Mode
VREF Input Impedance		>10		MΩ	Buffered Reference Mode
		180		kΩ	Unbuffered Reference Mode. 0–VREF Output Range,
				kΩ	Input Impedance = RDAC
		90			Unbuffered Reference Mode. 0–2 VREF Output Range,
					Input Impedance = RDAC
Reference Feedthrough		–90		dB	Frequency = 10 kHz
Channel-to-Channel Isolation		–80		dB	Frequency = 10 kHz
OUTPUT CHARACTERISTICS5
Minimum Output Voltage6		0.001		V min	This is a measure of the minimum and maximum
Maximum Output Voltage6		VDD – 0.001		V max	drive capability of the output amplifier.
DC Output Impedance		0.5		Ω
Short Circuit Current		50		mA	VDD = +5 V
		20		mA	VDD = +3 V
Power-Up Time		2.5		µs	Coming Out of Power-Down Mode. VDD = +5 V
		5		µs	Coming Out of Power-Down Mode. VDD = +3 V
LOGIC INPUTS5			± 1	µA
Input Current					VDD = +5 V ± 10%
VIL, Input Low Voltage			0.8	V
			0.6	V	VDD = +3 V ± 10%
			0.5	V	VDD = +2.5 V
VIH, Input High Voltage	2.4			V	VDD = +5 V ± 10%
	2.1			V	VDD = +3 V ± 10%
	2.0			V	VDD = +2.5 V
Pin Capacitance		2	3.5	pF
LOGIC OUTPUT (SDO)5
VDD = +5 V ± 10%
Output Low Voltage			0.4	V	ISINK = 2 mA
Output High Voltage	4.0			V	ISOURCE = 2 mA
VDD = +3 V ± 10%
Output Low Voltage			0.4	V	ISINK = 2 mA
Output High Voltage	2.4			V	ISOURCE = 2 mA
Floating-State Leakage Current			1	µA	DCEN = GND
Floating State O/P Capacitance		3		pF	DCEN = GND
POWER REQUIREMENTS
VDD	2.5		5.5	V	IDD Specification Is Valid for All DAC Codes
IDD (Normal Mode)				µA	Both DACs Active and Excluding Load Currents
VDD = +4.5 V to +5.5 V		300	450		Both DACs in Unbuffered Mode. VIH = VDD and
VDD = +2.5 V to +3.6 V		230	350	µA	VIL = GND. In Buffered Mode, extra current is
IDD (Full Power-Down)					typically x µA per DAC where x = 5 µA + VREF/RDAC.
				µA
VDD = +4.5 V to +5.5 V		0.2	1
VDD = +2.5 V to +3.6 V		0.05	1	µA

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NOTES

1See Terminology.

2Temperature range: B Version: –40°C to +105°C. 3DC specifications tested with the outputs unloaded.

4Linearity is tested using a reduced code range: AD5303 (Code 8 to 248); AD5313 (Code 28 to 995); AD5323 (Code 115 to 3981). 5Guaranteed by design and characterization, not production tested.

6In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V REF = VDD and “Offset plus Gain” Error must be positive.

Specifications subject to change without notice.

1	(VDD = +2.5 V to +5.5 V; RL = 2 k to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless
AC CHARACTERISTICS	otherwise noted.)
Parameter2			B Version3
		Min	Typ	Max	Units	Conditions/Comments
Output Voltage Settling Time					s	VREF = VDD = +5 V
AD5303			6	8		1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex)
AD5313			7	9	s	1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex)
AD5323			8	10	s	1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex)
Slew Rate			0.7		V/ s
Major-Code Transition Glitch Energy			12		nV-s	1 LSB Change Around Major Carry
						(011 . . . 11 to 100 . . . 00)
Digital Feedthrough			0.10		nV-s
Analog Crosstalk			0.01		nV-s
DAC-to-DAC Crosstalk			0.01		nV-s	VREF = 2 V ± 0.1 V p-p. Unbuffered Mode
Multiplying Bandwidth			200		kHz
Total Harmonic Distortion			–70		dB	VREF = 2.5 V ± 0.1 V p-p. Frequency = 10 kHz

NOTES

1Guaranteed by design and characterization, not production tested.

2See Terminology.

3Temperature range: B Version: –40°C to +105°C.

Specifications subject to change without notice.

TIMING CHARACTERISTICS1, 2, 3 (VDD = +2.5 V to +5.5 V; all specifications TMIN to TMAX unless otherwise noted.)

	Limit at TMIN, TMAX
Parameter	(B Version)	Units	Conditions/Comments
t1	33	ns min	SCLK Cycle Time
t2	13	ns min	SCLK High Time
t3	13	ns min	SCLK Low Time
t4	0	ns min	SYNC to SCLK Rising Edge Setup Time
t5	5	ns min	Data Setup Time
t6	4.5	ns min	Data Hold Time
t7	0	ns min	SCLK Falling Edge to SYNC Rising Edge
t8	100	ns min	Minimum SYNC High Time
t9	20	ns min	LDAC Pulsewidth
t10	20	ns min	SCLK Falling Edge to LDAC Rising Edge
t11	20	ns min	CLR Pulsewidth
t124, 5	5	ns min	SCLK Falling Edge to SDO Invalid
t134, 5	20	ns max	SCLK Falling Edge to SDO Valid
t145	0	ns min	SCLK Falling Edge to SYNC Rising Edge
t155	10	ns min	SYNC Rising Edge to SCLK Rising Edge

NOTES

1Guaranteed by design and characterization, not production tested.

2All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3See Figures 1 and 2.

4These are measured with the load circuit of Figure 1. 5Daisy-Chain Mode only (see Figure 45).

Specifications subject to change without notice.

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AD5303/AD5313/AD5323

2mAIOL

TO	+1.6V
OUTPUT
PIN	CL

50pF
2mA	IOH

Figure 1. Load Circuit for Digital Output (SDO) Timing Specifications

		t1
SCLK
t8	t3	t2	t7
	t4
SYNC
	t6
	t5
DIN*	DB15		DB0
			t9
LDAC
			t10
LDAC

t11

CLR

*SEE PAGE 12 FOR DESCRIPTION OF INPUT REGISTER

Figure 2. Serial Interface Timing Diagram

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ABSOLUTE MAXIMUM RATINGS1, 2

(TA = +25°C unless otherwise noted)

VDD to GND . . . . . . . . . . . . . . . . . . . . .	. . . . . –0.3 V to +7 V
Digital Input Voltage to GND . . . . . . .	–0.3 V to VDD + 0.3 V
Digital Output Voltage to GND . . . . .	–0.3 V to VDD + 0.3 V
Reference Input Voltage to GND . . . .	–0.3 V to VDD + 0.3 V
VOUTA, VOUTB to GND . . . . . . . . . . .	–0.3 V to VDD + 0.3 V
Operating Temperature Range	–40°C to +105°C
Industrial (B Version) . . . . . . . . . . . .
Storage Temperature Range . . . . . . . . .	. . . –65°C to +150°C
Junction Temperature (TJ Max) . . . . . .	. . . . . . . . . . .+150°C
16-Lead TSSOP Package	(TJ Max – TA)/θJA
Power Dissipation . . . . . . . . . . . . . . .
θJA Thermal Impedance . . . . . . . . . . .	. . . . . . . . . 160°C/W
Lead Temperature, Soldering	+215°C
Vapor Phase (60 sec) . . . . . . . . . . .
Infrared (15 sec) . . . . . . . . . . . . . . .	. . . . . . . . . . .+220°C

NOTES

1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

PIN CONFIGURATION

CLR							SDO
		1				16
LDAC							GND
		2	AD5303/			15
VDD							DIN
		3	AD5313/			14
VREFB		4	AD5323			13	SCLK
V	A		TOP VIEW
		5	(Not to Scale)			12	SYNC
REF							VOUTB
VOUTA
		6				11
BUF A							PD
		7				10
BUF B							DCEN
		8				9

Model	Temperature Range	Package Description	Package Option
AD5303BRU	–40°C to +105°C	Thin Shrink Small Outline Package (TSSOP)	RU-16
AD5313BRU	–40°C to +105°C	Thin Shrink Small Outline Package (TSSOP)	RU-16
AD5323BRU	–40°C to +105°C	Thin Shrink Small Outline Package (TSSOP)	RU-16

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5303/AD5313/AD5323 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

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AD5303/AD5313/AD5323

		PIN FUNCTION DESCRIPTIONS
Pin No.	Mnemonic	Function
1	CLR	Active low control input that loads all zeroes to both input and DAC registers.
2	LDAC	Active low control input that transfers the contents of the input registers to their respective DAC
		registers. Pulsing this pin low allows either or both DAC registers to be updated if the input regis-
		ters have new data. This allows simultaneous update of both DAC outputs
3	VDD	Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and the supply should be
		decoupled to GND.
4	VREFB	Reference Input Pin for DAC B. This is the reference for DAC B. It may be configured as a buff-
		ered or an unbuffered input, depending on the state of the BUF B pin. It has an input range from
		0 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode.
5	VREFA	Reference Input Pin for DAC A. This is the reference for DAC A. It may be configured as a
		buffered or an unbuffered input depending on the state of the BUF A pin. It has an input range
		from 0 to VDD in unbuffered mode and from 1 V to VDD in buffered mode.
6	VOUTA	Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
7	BUF A	Control pin that controls whether the reference input for DAC A is unbuffered or buffered. If this
		pin is tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered.
8	BUF B	Control pin that controls whether the reference input for DAC B is unbuffered or buffered. If this
		pin is tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered.
9	DCEN	This pin is used to enable the daisy-chaining option. This should be tied high if the part is being
		used in a daisy-chain. The pin should be tied low if it is being used in stand-alone mode.
10	PD	Active low control input that acts as a hardware power-down option. This pin overrides any soft-
		ware power-down option. Both DACs go into power-down mode when this pin is tied low. The
		DAC outputs go into a high impedance state and the current consumption of the part drops to
		200 nA @ 5 V (50 nA @ 3 V).
11	VOUTB	Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
12	SYNC	Active Low Control Input. This is the frame synchronization signal for the input data. When
		SYNC goes low, it powers-on the SCLK and DIN buffers and enables the input shift register. Data
		is transferred in on the falling edges of the following 16 clocks. If SYNC is taken high before the
		16th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is
		ignored by the device.
13	SCLK	Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
		input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered-down
		after each write cycle.
14	DIN	Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the
		falling edge of the serial clock input. The DIN input buffer is powered-down after each write cycle.
15	GND	Ground reference point for all circuitry on the part.
16	SDO	Serial Data Output that can be used for daisy-chaining a number of these devices together or for
		reading back the data in the shift register for diagnostic purposes. The serial data output is valid on
		the falling edge of the clock.

TERMINOLOGY

RELATIVE ACCURACY

For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the actual endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 5.

DIFFERENTIAL NONLINEARITY

Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 8.

OFFSET ERROR

This is a measure of the offset error of the DAC and the output amplifier. It is expressed as a percentage of the full-scale range.

GAIN ERROR

This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range.

OFFSET ERROR DRIFT

This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/°C.

GAIN ERROR DRIFT

This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C.

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