ANALOG DEVICES AD1939 Service Manual

FEATURES

PLL generated or direct master clock Low EMI design

112 dB DAC/107 dB ADC dynamic range and SNR −94 dB THD + N

Single 3.3 V supply Tolerance for 5 V logic inputs

Supports 24-bits and 8 kHz to 192 kHz sample rates Differential ADC input

Differential DAC output

Log volume control with autoramp function SPI controllable for flexibility Software-controllable clickless mute Software power-down

Right-justified, left-justified, I2S, and TDM modes Master and slave modes up to 16-channel input/output 64-lead LQFP package

Qualified for automotive applications

APPLICATIONS

Automotive audio systems

Home Theater Systems

Set-top boxes

Digital audio effects processors

4 ADC/8 DAC with PLL,

192 kHz, 24-Bit Codec

AD1939

GENERAL DESCRIPTION

The AD1939 is a high performance, single-chip codec that provides four analog-to-digital converters (ADCs) with differential input, and eight digital-to-analog converters (DACs) with differential output using the Analog Devices, Inc. patented multibit sigma-delta (Σ-Δ) architecture. An SPI port is included, allowing a microcontroller to adjust volume and many other parameters. The AD1939 operates from 3.3 V digital and analog supplies. The AD1939 is available in a 64-lead (differential output) LQFP package.

The AD1939 is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the master clock from the LR clock or from an external crystal, the AD1939 eliminates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. The DACs and ADCs are designed using the latest Analog Devices continuous time architectures to further minimize EMI. By using 3.3 V supplies, power consumption is minimized, further reducing emissions.

FUNCTIONAL BLOCK DIAGRAM

		DIGITAL AUDIO
		INPUT/OUTPUT
	AD1939	SERIAL DATA PORT
					DAC
					DAC
	ADC	SDATA	SDATA		DAC
		OUT	IN	DIGITAL
ANALOG	ADC		CLOCKS		DAC	ANALOG
		DIGITAL		FILTER
AUDIO				AND		AUDIO
		FILTER
INPUTS	ADC			VOLUME	DAC	OUTPUTS
		TIMING MANAGEMENT		CONTROL
	ADC	AND CONTROL			DAC
		(CLOCK AND PLL)
					DAC
					DAC
	PRECISION		SPI
		CONTROL PORT
	VOLTAGE
	REFERENCE
		CONTROL DATA				06071-001
		INPUT/OUTPUT

Figure 1.

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: [phone] www.analog.com Fax: [phone] ©2006–2011 Analog Devices, Inc. All rights reserved.

AD1939

TABLE OF CONTENTS
Features ..............................................................................................	1
Applications.......................................................................................	1
General Description .........................................................................	1
Functional Block Diagram ..............................................................	1
Revision History ...............................................................................	2
Specifications.....................................................................................	3
Test Conditions.............................................................................	3
Analog Performance Specifications ...........................................	3
Crystal Oscillator Specifications.................................................	4
Digital Input/Output Specifications...........................................	5
Power Supply Specifications........................................................	5
Digital Filters.................................................................................	6
Timing Specifications ..................................................................	6
Absolute Maximum Ratings............................................................	8
Thermal Resistance ......................................................................	8
ESD Caution..................................................................................	8
Pin Configuration and Function Descriptions.............................	9
Typical Performance Characteristics ...........................................	11
Theory of Operation ......................................................................	13
REVISION HISTORY
7/11—Rev. C to Rev. D
Changes to Pin 15, Pin 18, Pin 19, and Pin 20 Descriptions ......	9
Changes to Pin 26 and Pin 27 Descriptions................................	10
9/10—Rev. B to Rev. C
Added Qualified for Automotive Applications to the Features
Section................................................................................................	1
Changed Case Temperature from 130°C to 125°C ......................	4
Changed TA from −40°C to +130°C to −40°C to +105°C ...........	5
Changed TA from −40°C to +130°C to −40°C to +105°C ...........	7
Changes to Ordering Guide ..........................................................	31
Added Automotive Products Section ..........................................	31
3/10—Rev. A to Rev. B
Changes to Ordering Guide ..........................................................	31
6/07—Rev. 0 to Rev. A

Analog-to-Digital Converters (ADCs)....................................	13
Digital-to-Analog Converters (DACs) ....................................	13
Clock Signals...............................................................................	13
Reset and Power-Down .............................................................	14
Serial Control Port .....................................................................	14
Power Supply and Voltage Reference.......................................	15
Serial Data Ports—Data Format...............................................	15
Time-Division Multiplexed (TDM) Modes............................	15
Daisy-Chain Mode.....................................................................	19
Control Registers ............................................................................	24
Definitions...................................................................................	24
PLL and Clock Control Registers.............................................	24
DAC Control Registers..............................................................	25
ADC Control Registers..............................................................	27
Additional Modes.......................................................................	29
Application Circuits .......................................................................	30
Outline Dimensions.......................................................................	31
Ordering Guide ..........................................................................	31
Automotive Products.................................................................	31

Deleted I2C References.......................................................	Universal
Change to Figure 1 ............................................................................	1
Changes to Figure 2...........................................................................	9
Changes to Table 10 ..........................................................................	9
Changes to Table 11 .......................................................................	14
Changes to Table 12 .......................................................................	16
Changes to Figure 24 and Figure 25.............................................	22
Changes to Table 13 .......................................................................	23
Change to Figure 26 .......................................................................	23
Changes to Table 15 and Table 16 ................................................	24
Changes to Figure 27 and Figure 28.............................................	29
Change to Figure 30 .......................................................................	30
Updated Outline Dimensions.......................................................	31
Changes to Ordering Guide ..........................................................	31
7/06—Revision 0: Initial Version

Rev. D | Page 2 of 32

AD1939

SPECIFICATIONS

TEST CONDITIONS

Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.

Supply voltages (AVDD, DVDD)	3.3 V
Temperature range1	As specified in Table 1 and Table 2
Master clock	12.288 MHz (48 kHz fS, 256 × fS mode)
Input sample rate	48 kHz
Measurement bandwidth	20 Hz to 20 kHz
Word width	24 bits
Load capacitance (digital output)	20 pF
Load current (digital output)	±1 mA or 1.5 kΩ to ½ DVDD supply
Input voltage high	2.0 V
Input voltage low	0.8 V

1 Functionally guaranteed at −40°C to +125°C case temperature.

ANALOG PERFORMANCE SPECIFICATIONS

Specifications guaranteed at an ambient temperature of 25°C.

Table 1.

Parameter	Conditions/Comments	Min	Typ	Max	Unit
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution	All ADCs		24		Bits
Dynamic Range	20 Hz to 20 kHz, −60 dB input
No Filter (RMS)		96	102		dB
With A-Weighted Filter (RMS)		98	105		dB
Total Harmonic Distortion + Noise	−1 dBFS		−96	−87	dB
Full-Scale Input Voltage (Differential)			1.9		V rms
Gain Error		−10		+10	%
Interchannel Gain Mismatch		−0.25		+0.25	dB
Offset Error		−10	0	+10	mV
Gain Drift			100		ppm/°C
Interchannel Isolation			−110		dB
CMRR	100 mV rms, 1 kHz		55		dB
	100 mV rms, 20 kHz		55		dB
Input Resistance			14		kΩ
Input Capacitance			10		pF
Input Common-Mode Bias Voltage			1.5		V
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range	20 Hz to 20 kHz, −60 dB input
No Filter (RMS)		102	107		dB
With A-Weighted Filter (RMS)		105	110		dB
With A-Weighted Filter (Average)			112		dB
Total Harmonic Distortion + Noise	0 dBFS
	Two channels running		−94		dB
	Eight channels running		−86	−76	dB
Full-Scale Output Voltage			1.76 (4.96)		V rms (V p-p)
Gain Error		−10		+10	%
Interchannel Gain Mismatch		−0.2		+0.2	dB
Offset Error		−25	−6	+25	mV
Gain Drift		−30		+30	ppm/°C
Interchannel Isolation			100		dB

Rev. D | Page 3 of 32

AD1939

Parameter	Conditions/Comments	Min		Typ	Max		Unit
Interchannel Phase Deviation			0				Degrees
Volume Control Step			0.375				dB
Volume Control Range			95				dB
De-emphasis Gain Error					±0.6		dB
Output Resistance at Each Pin			100				Ω
REFERENCE
Internal Reference Voltage	FILTR pin		1.50				V
External Reference Voltage	FILTR pin	1.32	1.50		1.68		V
Common-Mode Reference Output	CM pin		1.50				V
REGULATOR
Input Supply Voltage	VSUPPLY pin	4.5	5		5.5		V
Regulated Output Voltage	VSENSE pin	3.19	3.37		3.55		V
Specifications measured at a case temperature of 125°C.
Table 2.
Parameter	Conditions/Comments	Min		Typ	Max		Unit
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution	All ADCs		24				Bits
Dynamic Range	20 Hz to 20 kHz, −60 dB input
No Filter (RMS)		93	102				dB
With A-Weighted Filter (RMS)		96	104				dB
Total Harmonic Distortion + Noise	−1 dBFS			−96	−87		dB
Full-Scale Input Voltage (Differential)			1.9				V rms
Gain Error		−10			+10		%
Interchannel Gain Mismatch		−0.25			+0.25		dB
Offset Error		−10	0		+10		mV
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range	20 Hz to 20 kHz, −60 dB input
No Filter (RMS)		101	107				dB
With A-Weighted Filter (RMS)		104	110				dB
With A-Weighted Filter (Average)			112				dB
Total Harmonic Distortion + Noise	0 dBFS
	Two channels running			−94			dB
	Eight channels running			−86	−70		dB
Full-Scale Output Voltage			1.76 (4.96)				V rms (V p-p)
Gain Error		−10			+10		%
Interchannel Gain Mismatch		−0.2			+0.2		dB
Offset Error		−25		−6	+25		mV
Gain Drift		−30			+30		ppm/°C
REFERENCE
Internal Reference Voltage	FILTR pin		1.50				V
External Reference Voltage	FILTR pin	1.32	1.50		1.68		V
Common-Mode Reference Output	CM pin		1.50				V
REGULATOR
Input Supply Voltage	VSUPPLY pin	4.5	5		5.5		V
Regulated Output Voltage	VSENSE pin	3.2	3.43		3.65		V

CRYSTAL OSCILLATOR SPECIFICATIONS

Table 3.

Parameter	Min	Typ	Max	Unit
Transconductance		3.5		mmhos

Rev. D | Page 4 of 32

						AD1939
DIGITAL INPUT/OUTPUT SPECIFICATIONS
−40°C < TA < +105°C, DVDD = 3.3 V ± 10%.
Table 4.
Parameter		Conditions/Comments	Min	Typ	Max		Unit
High Level Input Voltage (VIH)			2.0				V
		MCLKI/XI pin	2.2				V
Low Level Input Voltage (VIL)					0.8		V
Input Leakage		IIH @ VIH = 2.4 V			10		μA
		IIL @ VIL = 0.8 V			10		μA
High Level Output Voltage (VOH)		IOH = 1 mA	DVDD − 0.60				V
Low Level Output Voltage (VOL)		IOL = 1 mA			0.4		V
Input Capacitance					5		pF
POWER SUPPLY SPECIFICATIONS
Table 5.
Parameter		Conditions/Comments	Min	Typ	Max		Unit
SUPPLIES
Voltage		DVDD	3.0	3.3	3.6		V
		AVDD	3.0	3.3	3.6		V
		VSUPPLY	4.5	5.0	5.5		V
Digital Current		Master clock = 256 fS
Normal Operation		fS = 48 kHz		56			mA
		fS = 96 kHz		65			mA
		fS = 192 kHz		95			mA
Power-Down		fS = 48 kHz to 192 kHz		2.0			mA
Analog Current
Normal Operation				74			mA
Power-Down				23			mA
DISSIPATION
Operation		Master clock = 256 fS, 48 kHz
All Supplies				429			mW
Digital Supply				185			mW
Analog Supply				244			mW
Power-Down, All Supplies				83			mW
POWER SUPPLY REJECTION RATIO
Signal at Analog Supply Pins		1 kHz, 200 mV p-p		50			dB
		20 kHz, 200 mV p-p		50			dB

Rev. D | Page 5 of 32

AD1939

DIGITAL FILTERS

Table 6.

Parameter	Mode	Factor	Min	Typ	Max	Unit
ADC DECIMATION FILTER	All modes, typical @ 48 kHz
Pass Band		0.4375 fS		21		kHz
Pass-Band Ripple				±0.015		dB
Transition Band		0.5 fS		24		kHz
Stop Band		0.5625 fS		27		kHz
Stop-Band Attenuation			79			dB
Group Delay		22.9844/fS		479		μs
DAC INTERPOLATION FILTER
Pass Band	48 kHz mode, typical @ 48 kHz	0.4535 fS		22		kHz
	96 kHz mode, typical @ 96 kHz	0.3646 fS	35			kHz
	192 kHz mode, typical @ 192 kHz	0.3646 fS		70		kHz
Pass-Band Ripple	48 kHz mode, typical @ 48 kHz				±0.01	dB
	96 kHz mode, typical @ 96 kHz				±0.05	dB
	192 kHz mode, typical @ 192 kHz				±0.1	dB
Transition Band	48 kHz mode, typical @ 48 kHz	0.5 fS		24		kHz
	96 kHz mode, typical @ 96 kHz	0.5 fS		48		kHz
	192 kHz mode, typical @ 192 kHz	0.5 fS		96		kHz
Stop Band	48 kHz mode, typical @ 48 kHz	0.5465 fS		26		kHz
	96 kHz mode, typical @ 96 kHz	0.6354 fS		61		kHz
	192 kHz mode, typical @ 192 kHz	0.6354 fS		122		kHz
Stop-Band Attenuation	48 kHz mode, typical @ 48 kHz		70			dB
	96 kHz mode, typical @ 96 kHz		70			dB
	192 kHz mode, typical @ 192 kHz		70			dB
Group Delay	48 kHz mode, typical @ 48 kHz	25/fS		521		μs
	96 kHz mode, typical @ 96 kHz	11/fS		115		μs
	192 kHz mode, typical @ 192 kHz	8/fS		42		μs

TIMING SPECIFICATIONS

−40°C < TA < +105°C, DVDD = 3.3 V ± 10%.

Table 7.

Parameter	Condition	Comments	Min	Max	Unit
INPUT MASTER CLOCK (MCLK) AND
RESET
tMH	MCLK duty cycle	DAC/ADC clock source = PLL clock @ 256 fS, 384	40	60	%
		fS, 512 fS, and 768 fS
tMH		DAC/ADC clock source = direct MCLK @ 512 fS	40	60	%
		(bypass on-chip PLL)
fMCLK	MCLK frequency	PLL mode, 256 fS reference	6.9	13.8	MHz
fMCLK		Direct 512 fS mode		27.6	MHz
tPDR	Low		15		ns
tPDRR	Recovery	Reset to active output	4096		tMCLK
PLL
Lock Time	MCLK and LRCLK input			10	ms
256 fS VCO Clock, Output Duty Cycle,			40	60	%
MCLKO/XO Pin

Rev. D | Page 6 of 32

AD1939

Parameter	Condition			Comments	Min	Max	Unit
SPI PORT				See Figure 11
tCCH		CCLK high			35		ns
tCCL		CCLK low			35		ns
fCCLK		CCLK frequency		fCCLK = 1/tCCP; only tCCP shown in Figure 11		10	MHz
tCDS		CIN setup		To CCLK rising	10		ns
tCDH		CIN hold		From CCLK rising	10		ns
tCLS				To CCLK rising	10		ns
		CLATCH	setup
tCLH				From CCLK falling	10		ns
		CLATCH	hold
tCLHIGH				Not shown in Figure 11	10		ns
		CLATCH	high
tCOE		COUT enable		From CCLK falling		30	ns
tCOD		COUT delay		From CCLK falling		30	ns
tCOH		COUT hold		From CCLK falling, not shown in Figure 11	30		ns
tCOTS		COUT tristate		From CCLK falling		30	ns
DAC SERIAL PORT				See Figure 24
tDBH		DBCLK high		Slave mode	10		ns
tDBL		DBCLK low		Slave mode	10		ns
tDLS		DLRCLK setup		To DBCLK rising, slave mode	10		ns
tDLH		DLRCLK hold		From DBCLK rising, slave mode	5		ns
tDLS		DLRCLK skew		From DBCLK falling, master mode	−8	+8	ns
tDDS		DSDATA setup		To DBCLK rising	10		ns
tDDH		DSDATA hold		From DBCLK rising	5		ns
ADC SERIAL PORT				See Figure 25
tABH		ABCLK high		Slave mode	10		ns
tABL		ABCLK low		Slave mode	10		ns
tALS		ALRCLK setup		To ABCLK rising, slave mode	10		ns
tALH		ALRCLK hold		From ABCLK rising, slave mode	5		ns
tALS		ALRCLK skew		From ABCLK falling, master mode	−8	+8	ns
tABDD		ASDATA delay		From ABCLK falling		18	ns
AUXILIARY INTERFACE
tAXDS		AAUXDATA setup		To AUXBCLK rising	10		ns
tAXDH		AAUXDATA hold		From AUXBCLK rising	5		ns
tDXDD		DAUXDATA delay		From AUXBCLK falling		18	ns
tXBH		AUXBCLK high			10		ns
tXBL		AUXBCLK low			10		ns
tDLS		AUXLRCLK setup		To AUXBCLK rising	10		ns
tDLH		AUXLRCLK hold		From AUXBCLK rising	5		ns

Rev. D | Page 7 of 32

AD1939

ABSOLUTE MAXIMUM RATINGS

Table 8.

Parameter	Rating
Analog (AVDD)	−0.3 V to +3.6 V
Digital (DVDD)	−0.3 V to +3.6 V
VSUPPLY	−0.3 V to +6.0 V
Input Current (Except Supply Pins)	±20 mA
Analog Input Voltage (Signal Pins)	–0.3 V to AVDD + 0.3 V
Digital Input Voltage (Signal Pins)	−0.3 V to DVDD + 0.3 V
Operating Temperature Range (Case)	−40°C to +125°C
Storage Temperature Range	−65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA represents thermal resistance, junction-to-ambient; θJC represents the thermal resistance, junction-to-case. All characteristics are for a 4-layer board.

Table 9. Thermal Resistance

Package Type	θJA	θJC	Unit
64-Lead LQFP	47	11.1	°C/W

ESD CAUTION

Rev. D | Page 8 of 32

AD1939

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NC

NC

AVDD

LF

ADC2RN

ADC2RP

ADC2LN

ADC2LP

ADC1RN

ADC1RP

ADC1LN

ADC1LP

CM

AVDD

NC

NC

AGND 1

MCLKI/XI 2

MCLKO/XO 3

AGND 4

AVDD 5

OL3P 6

OL3N 7

OR3P 8

OR3N 9

OL4P 10

OL4N 11

OR4P 12

OR4N 13

PD/RST 14

DSDATA4 15

DGND 16

NC = NO CONNECT

64	63	62	61	60		59	58	57	56	55	54	53		52		51	50	49
																				AGND
																			48
																				FILTR
																			47
																				AGND
																			46
																				AVDD
																			45
																				AGND
																			44
																				OR2N
																			43
								AD1939												OR2P
																			42
																				OL2N
								TOP VIEW											41
							(Not to Scale)													OL2P
																			40
							DIFFERENTIAL
								OUTPUT											39	OR1N
																				OR1P
																			38
																				OL1N
																			37
																				OL1P
																			36
																			35		CLATCH
																				CCLK
																			34
																				DGND
																			33
17	18	19	20	21		22	23	24	25	26	27	28		29		30	31	32
DVDD	DSDATA3	DSDATA2	DSDATA1	DBCLK		DLRCLK	VSUPPLY	VSENSE	VDRIVE	ASDATA2	ASDATA1	ABCLK		ALRCLK		CIN	COUT	DVDD		06071-021

							Figure 2. 64-Lead LQFP, Differential Output, Pin Configuration
Table 10. Pin Function Descriptions
Pin No.	In/Out		Mnemonic					Description
1	I	AGND						Analog Ground.
2	I	MCLKI/XI						Master Clock Input/Crystal Oscillator Input.
3	O		MCLKO/XO					Master Clock Output/Crystal Oscillator Output.
4	I	AGND						Analog Ground.
5	I	AVDD						Analog Power Supply. Connect to analog 3.3 V supply.
6	O		OL3P					DAC 3 Left Positive Output.
7	O		OL3N					DAC 3 Left Negative Output.
8	O		OR3P					DAC 3 Right Positive Output.
9	O		OR3N					DAC 3 Right Negative Output.
10	O		OL4P					DAC 4 Left Positive Output.
11	O		OL4N					DAC 4 Left Negative Output.
12	O		OR4P					DAC 4 Right Positive Output.
13	O		OR4N					DAC 4 Right Negative Output
14	I							Power-Down Reset (Active Low).
			PD/RST
15	I/O		DSDATA4					DAC Serial Data Input 4. Data input to DAC4 data in/TDM DAC2 data out (dual-line
								mode)/AUX DAC2 data out (to external DAC2).
16	I	DGND						Digital Ground.
17	I	DVDD						Digital Power Supply. Connect to digital 3.3 V supply.
18	I/O		DSDATA3					DAC Serial Data Input 3. Data input to DAC3 data in/TDM DAC2 data in (dual-line
								mode)/AUX ADC2 data in (from external ADC2).
19	I/O		DSDATA2					DAC Serial Data Input 2. Data input to DAC2 data in/TDM DAC data out/AUX ADC1
								data in (from external ADC1).
20	I	DSDATA1						DAC Serial Data Input 1. Data input to DAC1 data in/TDM DAC data in/TDM data in.
21	I/O		DBCLK					Bit Clock for DACs.
22	I/O		DLRCLK					LR Clock for DACs.

Rev. D | Page 9 of 32

AD1939

Pin No.	In/Out		Mnemonic		Description
23	I	VSUPPLY			5 V Input to Regulator, Emitter of Pass Transistor.
24	I	VSENSE			3.3 V Output of Regulator, Collector of Pass Transistor.
25	O		VDRIVE		Drive for Base of Pass Transistor.
26	I/O		ASDATA2		ADC Serial Data Output 2. Data Output from ADC2/TDM ADC data in/AUX DAC1 data
					out (to external DAC1).
27	O		ASDATA1		ADC Serial Data Output 1. Data Output from ADC1/TDM ADC data out/TDM data out.
28	I/O		ABCLK		Bit Clock for ADCs.
29	I/O		ALRCLK		LR Clock for ADCs.
30	I		CIN		Control Data Input (SPI).
31	I/O		COUT		Control Data Output (SPI).
32	I	DVDD			Digital Power Supply. Connect to digital 3.3 V supply.
33	I	DGND			Digital Ground.
34	I	CCLK			Control Clock Input (SPI).
35	I				Latch Input for Control Data (SPI).
			CLATCH
36	O		OL1P		DAC 1 Left Positive Output.
37	O		OL1N		DAC 1 Left Negative Output.
38	O		OR1P		DAC 1 Right Positive Output.
39	O		OR1N		DAC 1 Right Negative Output.
40	O		OL2P		DAC 2 Left Positive Output.
41	O		OL2N		DAC 2 Left Negative Output.
42	O		OR2P		DAC 2 Right Positive Output.
43	O		OR2N		DAC 2 Right Negative Output.
44	I	AGND			Analog Ground.
45	I	AVDD			Analog Power Supply. Connect to analog 3.3 V supply.
46	I	AGND			Analog Ground.
47	O		FILTR		Voltage Reference Filter Capacitor Connection. Bypass with 10 μF||100 nF to AGND.
48	I	AGND			Analog Ground.
49		NC			No Connect.
50		NC			No Connect.
51	I	AVDD			Analog Power Supply. Connect to analog 3.3 V supply.
52	O		CM		Common-Mode Reference Filter Capacitor Connection. Bypass with
					47 μF||100 nF to AGND.
53	I		ADC1LP		ADC1 Left Positive Input.
54	I		ADC1LN		ADC1 Left Negative Input.
55	I		ADC1RP		ADC1 Right Positive Input.
56	I		ADC1RN		ADC1 Right Negative Input.
57	I		ADC2LP		ADC2 Left Positive Input.
58	I		ADC2LN		ADC2 Left Negative Input.
59	I		ADC2RP		ADC2 Right Positive Input.
60	I		ADC2RN		ADC2 Right Negative Input.
61	O	LF			PLL Loop Filter, Return to AVDD.
62	I	AVDD			Analog Power Supply. Connect to analog 3.3 V supply.
63		NC			No Connect.
64		NC			No Connect.

Rev. D | Page 10 of 32