Analog Devices AD5201BRM50-REEL7, AD5201BRM10-REEL7, AD5200BRM50-REEL7, AD5200BRM10-REEL7 Datasheet

a		256-Position and 33-Position
		Digital Potentiometers
		AD5200/AD5201

FEATURES AD5200—256-Position AD5201—33-Position 10 k , 50 k

3-Wire SPI-Compatible Serial Data Input Single Supply 2.7 V to 5.5 V or

Dual Supply 2.7 V for AC or Bipolar Operations

Internal Power-On Midscale Preset

APPLICATIONS

Mechanical Potentiometer Replacement

Instrumentation: Gain, Offset Adjustment

Programmable Voltage-to-Current Conversion

Programmable Filters, Delays, Time Constants

Line Impedance Matching

FUNCTIONAL BLOCK DIAGRAM

	VDD	AD5200/AD5201	VSS
			A
	CS		W
	CLK	SER	B
		REG
			RDAC
	SDI	8/6
		Dx	REG
	GND		SHDN
		PWR-ON
		PRESET

GENERAL DESCRIPTION

The AD5200 and AD5201 are programmable resistor devices, with 256 positions and 33 positions respectively, that can be digitally controlled through a 3-wire SPI serial interface. The terms programmable resistor, variable resistor (VR), and RDAC are commonly used interchangeably to refer to digital potentiometers. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. Both AD5200/AD5201 contain a single variable resistor in the compact µSOIC-10 package. Each device contains a fixed wiper resistance at the wiper contact that taps the programmable resistance at a point determined by a digital code. The code is loaded in the serial input register. The resistance between the wiper and either end point of the programmable resistor varies linearly with respect to the digital code transferred into the VR latch. Each variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper, or the B terminal and the wiper. The fixed A-to-B terminal resistance of 10 kΩ or 50 kΩ

has a nominal temperature coefficient of 500 ppm/°C. The VR has a VR latch that holds its programmed resistance value. The VR latch is updated from an SPI-compatible serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Eight data bits for the AD5200 and six data bits for the AD5201 make up the data word that is clocked into the serial input register. The internal preset forces the wiper to the midscale position by loading 80H and 10H into AD5200 and AD5201 VR latches respectively. The SHDN pin forces the resistor to an end-to-end open-circuit condition on the A terminal and shorts the wiper to the B terminal, achieving a microwatt power shutdown state. When SHDN is returned to logic high, the previous latch setting puts the wiper in the same resistance setting prior to shutdown. The digital interface is still active during shutdown so that code changes can be made that will produce a new wiper position when the device is returned from shutdown.

All parts are guaranteed to operate over the extended industrial temperature range of –40°C to +85°C.

REV. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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Fax: [phone]	© Analog Devices, Inc., 2001

AD5200/AD5201–SPECIFICATIONS

				(VDD = 5 V 10%, or 3 V 10%, VSS = 0 V, VA = +VDD, VB = 0 V,
AD5200 ELECTRICAL CHARACTERISTICS –40 C < TA < +85 C unless otherwise noted.)
Parameter			Symbol	Conditions			Min	Typ1	Max	Unit
DC CHARACTERISTICS RHEOSTAT MODE
Resistor Differential Nonlinearity 2			R-DNL	RWB, VA = No Connect			–1	± 0.25	+1	LSB
Resistor Integral Nonlinearity 2			R-INL	RWB, VA = No Connect			–2	± 0.5	+2	LSB
Nominal Resistor Tolerance 3			∆RAB	TA = 25°C			–30		+30	%
Resistance Temperature Coefficient			RAB/∆T	VAB = VDD, Wiper = No Connect				500		ppm/°C
Wiper Resistance			RW	VDD = 5 V				50	100	Ω
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.)
Resolution			N				8	± 1/4		Bits
Differential Nonlinearity 4			DNL				–1		+1	LSB
Integral Nonlinearity 4			INL				–2	± 1/2	+2	LSB
Voltage Divider Temperature Coefficient			∆VW/∆T	Code = 80 H				5		ppm/°C
Full-Scale Error			VWFSE	Code = FF H			–1.5	–0.5	0	LSB
Zero-Scale Error			VWZSE	Code = 00 H			0	+0.5	+1.5	LSB
RESISTOR TERMINALS
Voltage Range 5			VA, B, W				VSS		VDD	V
Capacitance 6 A, B			CA, B	f = 1 MHz, Measured to GND, Code = 80	H			45		pF
Capacitance 6 W			CW	f = 1 MHz, Measured to GND, Code = 80	H			60		pF
Shutdown Supply Current 7			IDD_SD	VDD = 5.5 V				0.01	5	µA
Common-ModeLeakage			ICM	VA = VB = VDD/2				1		nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High			VIH				2.4			V
Input Logic Low			VIL						0.8	V
Input Logic High			VIH	VDD = 3 V, VSS = 0 V			2.1			V
Input Logic Low			VIL	VDD = 3 V, VSS = 0 V					0.6	V
Input Current			IIL	VIN = 0 V or 5 V					± 1	µA
InputCapacitance 6			CIL					5		pF
POWERSUPPLIES
Logic Supply			VLOGIC				2.7		5.5	V
Power Single-Supply Range			VDD RANGE	VSS = 0 V			–0.3		5.5	V
Power Dual-Supply Range			VDD/SS RANGE				± 2.3		± 2.7	V
Positive Supply Current			IDD	VIH = +5 V or VIL = 0 V				15	40	µA
Negative Supply Current			ISS	VSS = –5 V				15	40	µA
Power Dissipation 8			PDISS	VIH = +5 V or VIL = 0 V, VDD = +5 V, VSS = 0 V					0.2	mW
Power Supply Sensitivity			PSS	∆VDD = +5 V ± 10%, Code = Midscale			–0.01	0.001	+0.01	%/%
DYNAMIC CHARACTERISTICS 6, 9
Bandwidth –3 dB			BW_10 kΩ	RAB = 10 kΩ, Code = 80 H				600		kHz
			BW_50 kΩ	RAB = 50 kΩ, Code = 80 H				100		kHz
Total Harmonic Distortion			THDW	VA = 1 V rms, VB = 0 V, f = 1 kHz, R AB = 10 kΩ				0.003		%
VW Settling Time (10 kΩ/50 kΩ)			tS	VA = 5 V, VB = 0 V, ± 1 LSB Error Band				2/9		µs
Resistor Noise Voltage Density			eN_WB	RWB = 5 kΩ, RS = 0				9		nV√Hz

NOTES

1Typicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V.

2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W = VDD/R for both VDD = +2.7 V,

VSS = –2.7 V.

3VAB = VDD, Wiper (VW) = No connect.

4INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions.

5Resistor Terminals A, B, W have no limitations on polarity with respect to each other.

6Guaranteed by design and not subject to production test.

7Measured at the A terminal. A terminal is open-circuited in shutdown mode.

8PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 9All dynamic characteristics use VDD = 5 V, VSS = 0 V.

Specifications subject to change without notice.

–2–

REV. B

AD5200/AD5201

					(VDD = 5 V 10%, or 3 V 10%, VSS = 0 V, VA = +VDD, VB = 0 V,
AD5201 ELECTRICAL CHARACTERISTICS –40 C < TA < +85 C unless otherwise noted.)
Parameter				Symbol	Conditions			Min	Typ1	Max	Unit
DC CHARACTERISTICS RHEOSTAT MODE
Resistor Differential Nonlinearity 2				R-DNL	RWB, VA = No Connect			–0.5	± 0.05	+0.5	LSB
Resistor Integral Nonlinearity 2				R-INL	RWB, VA = No Connect			–1	± 0.1	+1	LSB
Nominal Resistor Tolerance 3				∆RAB	TA = 25°C			–30		+30	%
Resistance Temperature Coefficient				RAB/∆T	VAB = VDD, Wiper = No Connect				500		ppm/°C
Wiper Resistance				RW	VDD = 5 V				50	100	Ω
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.)
Resolution 4				N				6	± 0.01		Bits
Differential Nonlinearity 5				DNL				–0.5		+0.5	LSB
Integral Nonlinearity 5				INL				–1	± 0.02	+1	LSB
Voltage Divider Temperature Coefficient				∆VW/∆T	Code = 10 H				5		ppm/°C
Full-Scale Error				VWFSE	Code = 20 H			–1/2	–1/4	0	LSB
Zero-Scale Error				VWZSE	Code = 00 H			0	+1/4	+1/2	LSB
RESISTOR TERMINALS
Voltage Range 6				VA, B, W				VSS		VDD	V
Capacitance 7 A, B				CA, B	f = 1 MHz, Measured to GND, Code = 10	H			45		pF
Capacitance 7 W				CW	f = 1 MHz, Measured to GND, Code = 10	H			60		pF
Shutdown Supply Current 8				IDD_SD	VDD = 5.5 V				0.01	5	µA
Common-ModeLeakage				ICM	VA = VB = VDD/2				1		nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High				VIH				2.4			V
Input Logic Low				VIL						0.8	V
Input Logic High				VIH	VDD = 3 V, VSS = 0 V			2.1			V
Input Logic Low				VIL	VDD = 3 V, VSS = 0 V					0.6	V
Input Current				IIL	VIN = 0 V or 5 V					±1	µA
InputCapacitance 7				CIL					5		pF
POWERSUPPLIES
Logic Supply				VLOGIC				2.7		5.5	V
Power Single-Supply Range				VDD RANGE	VSS = 0 V			–0.3		5.5	V
Power Dual-Supply Range				VDD/SS RANGE				± 2.3		± 2.7	V
Positive Supply Current				IDD	VIH = +5 V or VIL = 0 V				15	40	µA
Negative Supply Current				ISS	VSS = –5 V				15	40	µA
Power Dissipation 9				PDISS	VIH = +5 V or VIL = 0 V, VDD = +5 V, VSS = –5 V					0.2	mW
Power Supply Sensitivity				PSS	∆VDD = +5 V ± 10%			–0.01	0.001	+0.01	%/%
DYNAMIC CHARACTERISTICS 7, 10
Bandwidth –3 dB				BW_10 kΩ	RAB = 10 kΩ, Code = 10 H				600		kHz
				BW_50 kΩ	RAB = 50 kΩ, Code = 10 H				100		kHz
Total Harmonic Distortion				THDW	VA = 1 V rms, VB = 0 V, f = 1 kHz, R AB = 10 kΩ				0.003		%
VW Settling Time (10 kΩ/50 kΩ)				tS	VA = 5 V, VB = 0 V, ± 1 LSB Error Band				2/9		µs
Resistor Noise Voltage Density				eN_WB	RWB = 5 kΩ, RS = 0				9		nV√Hz

NOTES

1Typicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V.

2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W = VDD/R for both VDD = +2.7 V, VSS = –2.7 V.

3VAB = VDD, Wiper (VW) = No connect.

4Six bits are needed for 33 positions even though it is not a 64-position device.

5INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions.

6Resistor Terminals A, B, W have no limitations on polarity with respect to each other.

7Guaranteed by design and not subject to production test.

8Measured at the A terminal. A terminal is open-circuited in shutdown mode.

9PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

10All dynamic characteristics use VDD = 5 V, VSS = 0 V.

Specifications subject to change without notice.

REV. B

–3–

AD5200/AD5201–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS			(VDD = 5 V 10%, or 3 V 10%, VSS = 0 V, VA = +VDD, VB = 0 V, –40 C < TA < +85 C
			unless otherwise noted.)
Parameter		Symbol		Conditions	Min	Typ1	Max	Unit
INTERFACE TIMING CHARACTERISTICS (Applies to All Parts [Notes 2, 3])
Input Clock Pulsewidth		tCH, tCL		Clock Level High or Low	20			ns
Data Setup Time		tDS			5			ns
Data Hold Time		tDH			5			ns
CS Setup Time		tCSS			15			ns
CS High Pulsewidth		tCSW			40			ns
CLK Fall to CS Fall Hold Time		tCSH0			0			ns
CLK Fall to CS Rise Hold Time		tCSH1			0			ns
CS Rise to Clock Rise Setup		tCS1			10			ns

NOTES

1Typicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V.

2Guaranteed by design and not subject to production test.

3See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using VLOGIC = 5 V.

Specifications subject to change without notice.

SDI	1
	D7	D6	D5	D4	D3	D2	D1	D0
	0
CLK	1
	0
	1		DAC REGISTER LOAD
CS

0

1

VOUT

0

Figure 1a. AD5200 Timing Diagram

	1
SDI	D5	D4	D3	D2	D1	D0

0

1

CLK

0

1

DAC REGISTER LOAD

CS

0

1

VOUT

0

Figure 1b. AD5201 Timing Diagram

1

SDI

Dx

Dx

(DATA IN)

0

tCH

tDS

tDH

tCS1

1

CLK

0

tCSH0

tCL

tCSH1

1

t

CSS

CS

tCSW

0

tS

VDD

VOUT

0

1LSB

Figure 1c. Detail Timing Diagram

–4–

REV. B

AD5200/AD5201

ABSOLUTE MAXIMUM RATINGS1

(TA = 25°C, unless otherwise noted)

VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . 7 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . –0.3, +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 0 V, –7 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . .	. . . . . VSS, VDD
IMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . ± 20 mA2
Digital Inputs and Output Voltage to GND .	. . . . . . 0 V, 7 V
Operating Temperature Range . . . . . . . . . . .	–40°C to +85°C
Maximum Junction Temperature (TJ Max) . .	. . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . .	–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . .	. . . . . . . 300°C
Thermal Resistance θJA, µSOIC-10 . . . . . . . .	. . . . . 200°C/W

Package Power Dissipation = (TJ Max – TA)/θJA

NOTES

1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2Max current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. Please refer to TPC 31 and TPC 32 for detail.

PIN FUNCTION DESCRIPTIONS

Pin	Name	Description
1	B	B Terminal.
2	VSS	Negative Power Supply, specified for opera-
		tion from 0 V to –2.7 V.
3	GND	Ground.
4	CS	Chip Select Input, Active Low. When CS
		returns high, data will be loaded into the
		DAC register.
5	SDI	Serial Data Input.
6	CLK	Serial Clock Input, positive edge triggered.
7	SHDN	Active Low Input. Terminal A open circuit.
		Shutdown controls Variable Resistors of
		RDAC to temporary infinite.
8	VDD	Positive Power Supply (Sum of VDD + VSS
		≤ 5.5 V).
9	W	Wiper Terminal.
10	A	A Terminal.

PIN CONFIGURATION

B 1

10 A

	VSS	2	AD5200/	9	W
	GND	3	AD5201	8	VDD
	CS		TOP VIEW		SHDN
		4		7
			(Not to Scale)
	SDI				CLK
		5		6

ORDERING GUIDE

			Temperature	Package	Package	Full	Branding
Model	RES	k	Range	Description	Option	Reel Qty.	Information
AD5200BRM10-REEL7	256	10	–40°C/+85°C	SOIC-10	RM-10	5000	DLA
AD5200BRM50-REEL7	256	50	–40°C/+85°C	SOIC-10	RM-10	5000	DLB
AD5201BRM10-REEL7	33	10	–40°C/+85°C	SOIC-10	RM-10	5000	DMA
AD5201BRM50-REEL7	33	50	–40°C/+85°C	SOIC-10	RM-10	5000	DMB

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5200/AD5201 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. B

–5–