Analog Devices AD2S83IP, AD2S83AP Datasheet

a		Variable Resolution,
		Resolver-to-Digital Converter
		AD2S83

FEATURES

Tracking R/D Converter

High Accuracy Velocity Output

High Max Tracking Rate 1040 RPS (10 Bits) 44-Lead PLCC Package

10-, 12-, 14or 16-Bit Resolution Set by User Ratiometric Conversion

Stabilized Velocity Reference Dynamic Performance Set by User Industrial Temperature Range

APPLICATIONS

DC and AC Servo Motor Control

Process Control

Numerical Control of Machine Tools

Robotics

Axis Control

FUNCTIONAL BLOCK DIAGRAM

REFERENCE	OFFSET ADJUST
I/P

			HF FILTER			C3		+12V	R9	–12V
			C1	R2		R3			R8
			R1	C2					BANDWIDTH
									SELECTION
							R4
		AC ERROR O/P						INTEGRATOR		C5
						DEMOD			I/P	R5
						O/P
										C4
SIN	A1
SIG	SEGMENT	R – 2R DAC	A3			PHASE
GND	SWITCHING				SENSITIVE		INTEGRATOR			VELOCITY
					DETECTOR
COS	A2							O/P		SIGNAL
GND			AD2S83						R6
										TRACKING
RIPPLE
	16-BIT UP/DOWN COUNTER							VCO		RATE
CLOCK								I/P		SELECTION
+12V						VCO + DATA			C7
						TRANSFER
	OUTPUT DATA LATCH
–12V						LOGIC		VCO
									R7
								O/P
									3K3

DATA SC1 SC2 ENABLE		BYTE +5V DIG BUSY DIRECTION INHIBIT					C6
LOAD	16	SELECT	GND				390pF

DATA BITS

GENERAL DESCRIPTION

The AD2S83 is a monolithic 10-, 12-, 14or 16-bit tracking resolver-to-digital converter.

The converter allows users to select their own resolution and dynamic performance with external components. The converter allows users to select the resolution to be 10, 12, 14 or 16 bits and to track resolver signals rotating at up to 1040 revs per second (62,400 rpm) when set to 10-bit resolution.

The AD2S83 converts resolver format input signals into a parallel natural binary digital word using a ratiometric tracking conversion method. This ensures high noise immunity and tolerance of long leads allowing the converter to be located remote from the resolver.

The position output from the converter is presented via 3-state

output pins which can be configured for operations with 8- or 16-bit bus. BYTE SELECT, ENABLE and INHIBIT pins

ensure easy data transfer to 8- and 16-bit data bus, and outputs are provided to allow for cycle or pitch counting in external counters.

A precise analog signal proportional to velocity is also available and will replace a tachogenerator.

The AD2S83 operates over reference frequencies in the range 0 Hz to 20,000 Hz.

REV. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

PRODUCT HIGHLIGHTS

High Accuracy Velocity Output. A precision analog velocity signal with a typical linearity of ±0.1% and reversion error less than ±0.3% is generated by the AD2S83. The provision of this signal removes the need for mechanical tachogenerators used in servo systems to provide loop stabilization and speed control.

Resolution Set by User. Two control pins are used to select the resolution of the AD2S83 to be 10, 12, 14 or 16 bits allowing optimum resolution for each application.

Ratiometric Tracking Conversion. This technique provides continuous output position data without conversion delay. It also provides noise immunity and tolerance of harmonic distortion on the reference and input signals.

Dynamic Performance Set by the User. By selecting external resistor and capacitor values the user can determine bandwidth, maximum tracking rate and velocity scaling of the converter to match the system requirements. The component values are easy to select using the free component selection software design aid.

MODELS AVAILABLE

Information on the models available is given in the Ordering Guide.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: [phone]	World Wide Web Site: http://www.analog.com
Fax: [phone]	© Analog Devices, Inc., 1998

AD2S83–SPECIFICATIONS (6VS = 612 V dc 6 5%; VL = +5 V dc 6 10%; TA = –408C to +858C)

				AD2S83
Parameter		Conditions	Min	Typ	Max	Units
SIGNAL INPUTS (SIN, COS)
Frequency1			0		20,000	Hz
Voltage Level			1.8	2.0	2.2	V rms
Input Bias Current				60	150	nA
Input Impedance			1.0			MΩ
REFERENCE INPUT (REF)
Frequency			0		20,000	Hz
Voltage Level			1.0		8.0	V pk
Input Bias Current				60	150	nA
Input Impedance			1.0			MΩ
PERFORMANCE
Repeatability					1	LSB
Allowable Phase Shift		(Signals to Reference)	–10		+10	Degree
Max Tracking Rate		10 Bits	1040			rps
		12 Bits	260			rps
		14 Bits	65			rps
		16 Bits	16.25			rps
Bandwidth		User Selectable
ACCURACY					68 +1 LSB	arc min
Angular Accuracy		A, I
Monotonicity		Guaranteed Monotonic			4
Missing Codes (16-Bit Resolution)		A, I				Codes
VELOCITY SIGNAL
LINEARITY2, 3, 4
AD2S83AP		–40°C to +85°C		± 0.15	60.25	% FSR
	0 kHz–500 kHz
	0.5 MHz–1 MHz	–40°C to +85°C		± 0.25	61.0	% FSR
AD2S83IP		–40°C to +85°C		± 0.25	60.5
	0 kHz–500 kHz					% FSR
	0.5 MHz–1 MHz	–40°C to +85°C		± 0.25	61.0	% FSR
Reversion Error		–40°C to +85°C		± 0.5	61.0	% O/P
AD2S83AP
AD2S83IP		–40°C to +85°C		± 1.0	61.5	% O/P
DC Zero Offset5				± 3		mV
Gain Scaling Accuracy			± 8	± 1.5	63	% FSR
Output Voltage		1 mA Load				V
Dynamic Ripple		Mean Value			1.0	% rms O/P
INPUT/OUTPUT PROTECTION				± 8
Analog Inputs		Overvoltage Protection				V
Analog Outputs		Short Circuit O/P Protection	± 5.6	± 8	± 10.4	mA
DIGITAL POSITION
Resolution		10, 12, 14, and 16				Bits
Output Format		Bidirectional Natural Binary			3
Load						LSTTL
INHIBIT6
Sense		Logic LO to INHIBIT
Time to Stable Data			240	390	490	ns
ENABLE6		Logic LO Enables Position Output
ENABLE6/Disable Time		Logic HI Outputs in High
		Impedance State	35		110	ns
BYTE SELECT6
Sense
Logic HI		MS Byte DB1–DB8
Logic LO		LS Byte DB1–DB8
Time to Data Available			60		140	ns
SHORT CYCLE INPUTS		Internally Pulled High via
SC1	SC2	100 kΩ to +VS
0	0	10-Bit Resolution
0	1	12-Bit Resolution
1	0	14-Bit Resolution
1	1	16-Bit Resolution

–2–

REV. D

					AD2S83
			AD2S83
Parameter	Conditions	Min	Typ	Max	Units
COMPLEMENT	Internally Pulled High via 100 kΩ
	to +VS. Logic LO to Activate;
	No Connect for Normal Operation
DATA LOAD	Internally Pulled High via 100 kΩ
Sense			150	300	ns
	to +VS. Logic LO Allows
	Data to be Loaded into the
	Counters from the Data Lines
BUSY6, 7
Sense	Logic HI When Position O/P Changing	150		350
Width					ns
Load	Use Additional Pull-Up (See Figure 2)			1	LSTTL
DIRECTION6
Sense	Logic HI Counting Up
Max Load	Logic LO Counting Down			3	LSTTL
RIPPLE CLOCK6
Sense	Logic HI
	All 1s to All 0s
	All 0s to All 1s	300
Width	Dependent on Input Velocity				ns
Reset	Before Next Busy			3
Load					LSTTL
DIGITAL INPUTS	INHIBIT, ENABLE	2.0			V
Input High Voltage, VIH
	DB1–DB16, Byte Select
	±VS = ± 11.4 V, VL = 5.0 V			0.8
Input Low Voltage, VIL	INHIBIT, ENABLE				V
	DB1–DB16, Byte Select
	±VS = ± 12.6 V, VL = 5.0 V
DIGITAL INPUTS	INHIBIT, ENABLE			6100	µA
Input High Current, IIH
	DB1–DB16
	±VS = ± 12.6 V, VL = 5.5 V			6100	µA
Input Low Current, IIL	INHIBIT, ENABLE
	DB1–DB16, Byte Select
	±VS = ± 12.6 V, VL = 5.5 V
DIGITAL INPUTS				1.0
Low Voltage, VIL	ENABLE = HI				V
	SC1, SC2, DATA LOAD
	±VS = ± 12.0 V, VL = 5.0 V			–400	µA
Low Current, IIL	ENABLE = HI
	SC1, SC2, DATA LOAD
	±VS = ± 12.0 V, VL = 5.0 V
DIGITAL OUTPUTS		2.4
High Voltage, VOH	DB1–DB16				V
	RIPPLE CLK, DIR
	±VS = ± 12.0 V, VL = 4.5 V
Low Voltage, VOL	IOH = 100 µA			0.4
	DB1–DB16				V
	RIPPLE CLK, DIR
	±VS = ± 12.0 V, VL = 5.5 V
	IOL = 1.2 mA

NOTES

1Angular accuracy is not guaranteed <50 Hz reference frequency. 2Linearity derates from 500 kHz–1000 kHz @ 0.0017%/kHz.

3Refer to Definition of Linearity, “The AD2S83 as a Silicon Tachogenerator.” 4Worst case reversion error at temperature extremes.

5Velocity output offset dependent on value for R6.

6Refer to timing diagram.

7Busy pulse guaranteed up to a VCO rate of 900 kHz.

All min and max specifications are guaranteed. Specifications in Specifications subject to change without notice.

boldface are tested on all production units at final electrical test.

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–3–

AD2S83–SPECIFICATIONS (6VS = 612 V dc 6 5%; VL = +5 V dc 6 10%; TA = –408C to +858C)

AD2S83

Parameter

Conditions

Min

Typ

Max

Units

THREE-STATE LEAKAGE

DB1–DB16 Only

Current IL

± VS = ± 12.0 V, VL = 5.5 V

620

µA

VOL = 0 V

± VS = ±12.0 V, VL = 5.5 V

620

µA

VOH = 5.0 V

RATIO MULTIPLIER

AC Error Output Scaling

10 Bit

177.6

mV/Bit

12 Bit

44.4

mV/Bit

14 Bit

11.1

mV/Bit

16 Bit

2.775

mV/Bit

PHASE SENSITIVE DETECTOR

12

Output Offset Voltage

mV

Gain

In Phase

w.r.t. REF

–0.882

–0.9

–0.918

V rms/V dc

In Quadrature

w.r.t. REF

± 0.02

V rms/V dc

Input Bias Current

60

150

nA

Input Impedance

1.0

± 8

MΩ

Input Voltage

V

INTEGRATOR

Open-Loop Gain

At 10 kHz

57

60

63

dB

Dead Zone Current (Hysteresis)

90

100

110

nA/LSB

Input Offset Voltage

1

5

mV

Input Bias Current

68

60

150

nA

Output Voltage Range

V

VCO

Maximum Rate

1.1

MHz

VCO Rate

+ve DIR

8.25

8.50

8.75

kHz/µA

VCO Power Supply Sensitivity

–ve DIR

8.25

8.50

8.75

kHz/µA

+0.5

%/V

Rate

+VS

–VS

–0.5

%/V

Input Offset Voltage

3

50

mV

Input Bias Current

12

nA

Input Bias Current Tempco

+0.22

nA/°C

Linearity of Absolute Rate

AD2S83AP

± 0.15

60.25

0 kHz–500 kHz

% FSR

0.5 MHz–1 MHz

± 0.25

61.0

% FSR

AD2S83IP

± 0.25

60.5

0 kHz–500 kHz

% FSR

0.5 MHz–1 MHz

± 0.25

61.0

% FSR

Reversion Error

± 0.5

61.0

AD2S83AP

% Output

AD2S83IP

± 1.0

61.5

% Output

POWER SUPPLIES

Voltage Levels

+11.4

+12.6

V

+VS

–VS

–11.4

–12.6

V

+VL

+4.5

+5

+VS

V

Current

± VS @ ± 12 V

± 12

± IS

623

mA

± IS

± VS @ ± 12.6 V

± 19

630

mA

± IL

+VL @ ±5.0 V

± 0.5

61.5

mA

All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.

Specification subject to change without notice.

ORDERING GUIDE

Temperature

Package

Package

Model

Range

Accuracy

Description

Option

AD2S83AP

–40°C to +85°C

8 arc min

Plastic Leaded Chip Carrier

P-44A

AD2S83IP

–40°C to +85°C

8 arc min

Plastic Leaded Chip Carrier

P-44A

–4–

REV. D

AD2S83

ABSOLUTE MAXIMUM RATINGS1 (with respect to GND)

+VS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . +13 V dc
–VS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . –13 V dc
+VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . +VS
Reference . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . +13 V to –VS
SIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . +13 V to –VS
COS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . +13 V to –VS
Any Logical Input . . . . . . . . . . . . . . . . . .	–0.4 V dc to +VL dc
Demodulator Input . . . . . . . . . . . . . . . . . .	. . . . . +13 V to –VS
Integrator Input . . . . . . . . . . . . . . . . . . . . .	. . . . . +13 V to –VS
VCO Input . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . +13 V to –VS
Power Dissipation . . . . . . . . . . . . . . . . . . .	. . . . . . . . 800 mW
Operating Temperature	–40°C to +85°C
Industrial (AP, IP) . . . . . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . .	. –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . .	. . . . . . . . . +300°C

CAUTION

1Absolute Maximum Ratings are those values beyond which damage to the device may occur.

2Correct polarity voltages must be maintained on the +VS and –VS pins.

RECOMMENDED OPERATING CONDITIONS

Power Supply Voltage (+VS, –VS) . . . . . . . . . . ±12 V dc ± 5%

Power Supply Voltage VL . . . . . . . . . . . . . . . . . +5 V dc ± 10% Analog Input Voltage (SIN and COS) . . . . . . . .2 V rms ± 10%

Analog Input Voltage (REF) . . . . . . . . . . . . . . 1 V to 8 V peak Signal and Reference Harmonic Distortion . . . . . . . 10% (max) Phase Shift Between Signal and Reference . . . ±10 Degrees (max) Ambient Operating Temperature Range

Industrial (AP, IP) . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

PIN CONFIGURATION

		SIGNAL GND	ANALOG GND	COS I/P	AC ERROR O/P	REF I/P	DEMOD O/P	DEMOD I/P	INTEGRATOR I/P	INTEGRATOR O/P	VCO O/P	VCO I/P
	6		5	4	3	2	1	44	43	42	41	40
SIN I/P	7							PIN 1				39		–V
								IDENTIFIER						S
+VS	8											38		RIPPLE CLOCK
NC	9											37		DIRECTION
(MSB) DB1 10												36		BUSY
DB2 11						AD2S83						35		COMP
DB3 12						TOP VIEW						34		DATA LOAD
DB4 13					(Not to Scale)							33		SC1
DB5 14													32 SC2
DB6 15												31		DIGITAL GND
DB7 16													30 INHIBIT
DB8 17												29		NC
	18		19	20	21	22	23	24	25	26	27	28
		DB9	DB10	DB11	DB12	DB13	DB14	DB15	(LSB)DB16	+V	ENABLE	SELECTBYTE
										L

NC = NO CONNECT

ESD SENSITIVITY

PIN FUNCTION DESCRIPTIONS

Pin
Nos.	Mnemonic	Description
1	DEMOD O/P	Demodulator Output
2	REFERENCE I/P	Reference Signal Input
3	AC ERROR O/P	Ratio Multiplier Output
4	COS	Cosine Input
5	ANALOG GND	Power Ground
6	SIGNAL GND	Resolver Signal Ground
7	SIN	Sine Input
8	+VS	Positive Power Supply
10–25	DB1–DB16	Parallel Output Data
26	+VL	Logic Power Supply
27	ENABLE	Logic HI—Output Data Pins in
		High Impedance State
		Logic LO—Presents Active Data
		to the Output Pins
28	BYTE SELECT	Logic HI—Most Significant Byte to
		DB1–DB8
		Logic LO—Least Significant Byte
		to DB1–DB8
30	INHIBIT	Logic LO Inhibits Data Transfer
		to Output Latches
31	DIGITAL GND	Digital Ground
32, 33	SC2–SC1	Select Converter Resolution
34	DATA LOAD	Logic LO DB1–DB16 Inputs
		Logic HI DB1–DB16 Outputs
35	COMPLEMENT	Active Logic LO
36	BUSY	Converter Busy, Data not Valid
		While Busy HI
37	DIRECTION	Logic State Defines Direction of
		Input Signal Rotation
38	RIPPLE CLOCK	Positive Pulse When Converter Output
		Changes from 1s to All 0s or Vice Versa
39	–VS	Negative Power Supply
40	VCO I/P	VCO Input
41	VCO O/P	VCO Output
42	INTEGRATOR O/P	Integrator Output
43	INTEGRATOR I/P	Integrator Input
44	DEMOD I/P	Demodulator Input

The AD2S83 features an input protection circuit consisting of large “distributed” diodes and polysilicon series resistors to dissipate both high energy discharge (Human Body Model) and fast, low energy pulses (Charges Device Model).

Proper ESD protection are strongly recommended to avoid functional damage or performance degradation. For further information on ESD precautions, refer to Analog Devices ESD Prevention Manual.

WARNING!

ESD SENSITIVE DEVICE

REV. D

–5–

AD2S83

Bit Weight Table

Binary	Resolution	Degrees	Minutes	Seconds
Bits (N)	(NN)	/Bit	/Bit	/Bit
0	1	360.0	21600.0	1296000.0
1	2	180.0	10800.0	648000.0
2	4	90.0	5400.0	324000.0
3	8	45.0	2700.0	162000.0
4	16	22.5	1350.0	81000.0
5	32	11.25	675.0	40500.0
6	64	5.625	337.5	20250.0
7	128	2.8125	168.75	10125.0
8	256	1.40625	84.375	5062.5
9	512	0.703125	42.1875	2531.25
10	1024	0.3515625	21.09375	1265.625
11	2048	0.1757813	10.546875	632.8125
12	4096	0.0878906	5.273438	316.40625
13	8192	0.0439453	2.636719	158.20313
14	16384	0.0219727	1.318359	79.10156
15	32768	0.0109836	0.659180	39.55078
16	65536	0.0054932	0.329590	19.77539
17	131072	0.0027466	0.164795	9.88770
18	262144	0.0013733	0.082397	4.94385

CONNECTING THE CONVERTER

The power supply voltages connected to +VS and –VS pins should be +12 V dc and –12 V dc and must not be reversed. The voltage applied to VL can be +5 V dc to +VS.

It is recommended that the decoupling capacitors are connected in parallel between the power lines +VS, –VS and ANALOG GROUND adjacent to the converter. Recommended values are 100 nF (ceramic) and 10 F (tantalum). Also capacitors of

100 nF and 10 F should be connected between +VL and DIGITAL GROUND adjacent to the converter.

When more than one converter is used on a card, separate decoupling capacitors should be used for each converter.

The resolver connections should be made to the SIN and COS inputs, REFERENCE INPUT and SIGNAL GROUND as shown in Figure 11 and described in the Connecting the Resolver section.

The two signal ground wires from the resolver should be joined at the SIGNAL GROUND pin of the converter to minimize the coupling between the sine and cosine signals. For this reason it is also recommended that the resolver is connected using individually screened twisted pair cables with the sine, cosine and reference signals twisted separately.

SIGNAL GROUND and ANALOG GROUND are connected internally. ANALOG GROUND and DIGITAL GROUND must be connected externally and as close to the converter as possible.

The external components required should be connected as shown in Figure 1.

CONVERTER RESOLUTION

Two major areas of the AD2S83 specification can be selected by the user to optimize the total system performance. The resolution of the digital output is set by the logic state of the inputs SC1 and SC2 to be 10, 12, 14 or 16 bits; and the dynamic characteristics of bandwidth and tracking rate are selected by the choice of external components.

The choice of the resolution will affect the values of R4 and R6 which scale the inputs to the integrator and the VCO respectively (see Component Selection section). If the resolution is changed, then new values of R4 and R6 must be switched into the circuit.

Note: When changing resolution under dynamic conditions, do it when the BUSY is low, i.e., when data is not changing.

REFERENCE	OFFSET ADJUST
I/P

			HF FILTER		C3		+12V	R9	–12V
			C1	R2		R3		R8
			R1	C2				BANDWIDTH
								SELECTION
						R4
		AC ERROR O/P					INTEGRATOR		C5
								I/P
						DEMOD			R5
						O/P
SIN	A1								C4
					PHASE
SIG GND									VELOCITY
	SEGMENT	R - 2R DAC	A3		SENSITIVE
						INTEGRATOR			SIGNAL
	SWITCHING				DETECTOR
COS	A2						O/P
GND			AD2S83					R6	TRACKING
RIPPLE							VCO		RATE
	16-BIT UP/DOWN COUNTER								SELECTION
CLOCK							I/P
					VCO + DATA			C7
					TRANSFER
+12V								150pF
					LOGIC
	OUTPUT DATA LATCH
–12V							VCO
							O/P	R7
								3K3

DATA SC1 SC2 ENABLE	16 DATA BITS	BYTE	+5V DIG BUSY DIRECTION INHIBIT	C6
LOAD		SELECT	GND	390pF

Figure 1. Connection Diagram

–6–

REV. D