Texas Instruments THS5641AIPWR, THS5641AIPW, THS5641AIDWR, THS5641AIDW Datasheet

								THS5641A
				8-BIT, 100 MSPS, CommsDAC
		DIGITAL-TO-ANALOG CONVERTER
							SLAS277 ±MARCH 2000
D Member of the Pin-Compatible	SOIC (DW) OR TSSOP (PW) PACKAGE
CommsDAC Product Family					(TOP VIEW)
D 100 MSPS Update Rate
	D7			1	28			CLK
D 8-Bit Resolution	D6			2	27			DVDD
D Signal-to-Noise and Distortion Ratio	D5			3	26			DGND
				4	25
(SINAD) at 5 MHz: 50 dB	D4							MODE
	D3			5	24			AVDD
D Integral Nonlinearity INL: 0.25 LSB
	D2			6	23			COMP2
D Differential Nonlinearity DNL: 0.25 LSB	D1			7	22			IOUT1
D 1 ns Setup/Hold Time	D0			8	21			IOUT2
D Glitch Energy: 5 pV-s	NC			9	20			AGND
	NC			10	19			COMP1
D Settling Time to 0.1%: 35 ns	NC			11	18			BIASJ
D Differential Scalable Current Outputs: 2 mA	NC			12	17			EXTIO
to 20 mA	NC			13	16			EXTLO
D On-Chip 1.2-V Reference	NC			14	15			SLEEP

D 3-V and 5-V Single Supply Operation

NC ± No internal connection

DStraight Binary or Twos Complement Input

DPower Dissipation: 100 mW at 3.3 V, Sleep Mode: 17 mW at 3.3 V

DPackage: 28-Pin SOIC and TSSOP

description

The THS5641A is an 8-bit resolution digital-to-analog converter (DAC) optimized for video applications and digital data transmission in wired and wireless communication systems. The 8-bit DAC is a member of the CommsDAC series of high-speed, low-power CMOS digital-to-analog converters. The CommsDAC family consists of pin compatible 14-, 12-, 10-, and 8-bit DACs. All devices offer identical interface options, small outline package and pinout. The THS5641A offers superior ac and dc performance while supporting update rates up to 100 MSPS.

The THS5641A operates from an analog and digital supply of 3 V to 5.5 V. Its inherent low power dissipation of 100 mW ensures that the device is well suited for portable and low power applications. Lowering the full-scale current output reduces the power dissipation without significantly degrading performance. The device features a SLEEP mode, which reduces the standby power to approximately 17 mW, thereby optimizing the power consumption for system needs.

The THS5641A is manufactured in Texas Instruments advanced high-speed mixed-signal CMOS process. A current-source-array architecture combined with simultaneous switching shows excellent dynamic performance. On-chip edge-triggered input latches and a 1.2 V temperature compensated bandgap reference provide a complete monolithic DAC solution. The digital supply range of 3 V to 5.5 V supports 3 V and 5 V CMOS logic families. Minimum data input setup and hold times allow for easy interfacing with external logic. The THS5641A supports both a straight binary and twos complement input word format, enabling flexible interfacing with digital signal processors.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

CommsDAC is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 2000, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

THS5641A

8-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS277 ±MARCH 2000

description (continued)

The THS5641A provides a nominal full-scale differential output current of 20 mA and >300 kΩ output impedance, supporting both single-ended and differential applications. The output current can be directly fed to the load (e.g., external resistor load or transformer), with no additional external output buffer required. An accurate on-chip reference and control amplifier allows the user to adjust this output current from 20 mA down to 2 mA, with no significant degradation of performance. This reduces power consumption and provides 20 dB gain range control capabilities. Alternatively, an external reference voltage and control amplifier may be applied in applications using a multiplying DAC.

The THS5641A is available in both a 28-pin SOIC and TSSOP package. The device is characterized for operation over the industrial temperature range of ±40°C to 85°C.

AVAILABLE OPTIONS

	PACKAGE
TA
	28-TSSOP	28-SOIC
	(PW)	(DW)
± 40°C to 85°C	THS5641AIPW	THS5641AIDW

functional block diagram

			C1	AVDD
	SLEEP	COMP1	0.1 µF	COMP2	0.1 µF
EXTLO	1.2 V
	REF

		1 nF			IOUT1
EXTIO	±			Output	50 Ω	RLOAD
CEXT			Current
			Source	Current
BIASJ	+	Control	Array	Switches
0.1 µF		AMP
I BIAS					IOUT2
2 kΩ RBIAS
DVDD					50 Ω	RLOAD

Logic

D[7:0]

Control

MODE

CLK

DGND

AGND

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

			THS5641A
			8-BIT, 100 MSPS, CommsDAC
			DIGITAL-TO-ANALOG CONVERTER
			SLAS277 ±MARCH 2000
			Terminal Functions
TERMINAL		I/O	DESCRIPTION
NAME	NO.
AGND	20	I	Analog ground return for the internal analog circuitry
AVDD	24	I	Positive analog supply voltage (3 V to 5.5 V)
BIASJ	18	O	Full-scale output current bias
CLK	28	I	External clock input. Input data latched on rising edge of the clock.
COMP1	19	I	Compensation and decoupling node, requires a 0.1 F capacitor to AVDD.
COMP2	23	I	Internal bias node, requires a 0.1 F decoupling capacitor to AGND.
D[7:0]	[1:8]	I	Data bits 0 through 7.
			D7 is most significant data bit (MSB), D0 is least significant data bit (LSB).
DGND	26	I	Digital ground return for the internal digital logic circuitry
DVDD	27	I	Positive digital supply voltage (3 V to 5.5 V)
EXTIO	17	I/O	Used as external reference input when internal reference is disabled (i.e., EXTLO = AVDD). Used as internal
			reference output when EXTLO = AGND, requires a 0.1 F decoupling capacitor to AGND when used as reference
			output
EXTLO	16	O	Internal reference ground. Connect to AVDD to disable the internal reference source
IOUT1	22	O	DAC current output. Full scale when all input bits are set 1
IOUT2	21	O	Complementary DAC current output. Full scale when all input bits are 0
MODE	25	I	Mode select. Internal pulldown. Mode 0 is selected if this pin is left floating or connected to DGND. See
			timing diagram.
NC	[9:14]	N	No connection
SLEEP	15	I	Asynchronous hardware power down input. Active High. Internal pulldown. Requires 5 s to power down but 3 ms
			to power up.

absolute maximum ratings over operating free-air temperature (unless otherwise noted)²

Supply voltage range, AVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . ±0.3 V to 6.5 V
DVDD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . ±0.3 V to 6.5 V
Voltage between AGND and DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . ±0.3 V to 0.5 V
Supply voltage range, AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . ±6.5 V to 6.5 V
CLK, SLEEP, MODE (see Note 2) . . . . . . . . . . . . . . . . . . . . . .	±0.3 V to DVDD + 0.3 V
Digital input D7±D0 (see Note 2) . . . . . . . . . . . . . . . . . . . . . .	±0.3 V to DVDD + 0.3 V
IOUT1, IOUT2 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±1 V to AVDD + 0.3 V
COMP1, COMP2 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . .	±0.3 V to AVDD + 0.3 V
EXTIO, BIASJ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.3 V to AVDD + 0.3 V
EXTLO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . ±0.3 V to 0.3 V
Peak input current (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . 20 mA
Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . ±30 mA
Operating free-air temperature range, TA: THS5641AI . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . ±40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . .	. . . . . . . . . . . . . . 260°C

² Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Measured with respect to AGND. 2. Measured with respect to DGND.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

THS5641A

8-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS277 ±MARCH 2000

electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA (unless otherwise noted)

dc specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

8

Bits

DC accuracy²

INL

Integral nonlinearity

TA = ±40°C to 85°C

±0.25

±0.1

0.25

LSB

DNL

Differential nonlinearity

±0.25

±0.05

0.25

LSB

Monotonicity

Monotonic

Analog output

Offset error

0.02

%FSR

Gain error

Without internal reference

2.3

%FSR

With internal reference

1.3

Full scale output current³

2

20

mA

Output compliance range

AVDD = 5 V,

IOUTFS = 20 mA

±1

1.25

V

AVDD = 3.3 V IOUTFS = 20 mA

±1

0.6

V

Output resistance

300

kΩ

Output capacitance

5

pF

Reference output

Reference voltage

1.18

1.22

1.32

V

Reference output current§

100

nA

Reference input

VEXTIO

Input voltage range

0.1

1.25

V

Input resistance

1

MΩ

Small signal bandwidth¶

Without CCOMP1

1.3

MHz

Input capacitance

100

pF

Temperature coefficients

Offset drift

0

Gain drift

Without internal reference

±40

ppm of

With internal reference

±120

FSR/°C

Reference voltage drift

±35

Power supply

AVDD

Analog supply voltage

3

5.5

V

DVDD

Digital supply voltage

3

5.5

V

IAVDD

Analog supply current

25

30

mA

Sleep mode supply current

Sleep mode

3

5

mA

I

Digital supply current#

5

6

mA

DVDD

Power dissipation||

AVDD = 5 V,

DVDD = 5 V

IOUTFS = 20 mA

175

mW

AVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA

100

AVDD

Power supply rejection ratio

±0.4

%FSR/V

DVDD

±0.025

Operating range

±40

85

°C

² Measured at IOUT1 in virtual ground configuration.

³ Nominal full-scale current IOUTFS equals 32X the IBIAS current.

§ Use an external buffer amplifier with high impedance input to drive any external load.

¶ Reference bandwidth is a function of external cap at COMP1 pin and signal level.

# Measured at f

CLK

= 50 MSPS and f

OUT

= 1 MHz.

|| Measured for 50

Ω R

LOAD

at IOUT1 and IOUT2, f

CLK

= 50 MSPS and f

OUT

= 20 MHz.

Specifications subject to change

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

THS5641A 8-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS277 ±MARCH 2000

electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA, single-ended output IOUT1, 50 Ω doubly terminated load (unless otherwise noted)

ac specifications

	PARAMETER		TEST CONDITIONS	MIN TYP MAX		UNIT
Analog output
fCLK	Maximum output update rate		DVDD = 4.5 V to 5.5 V	100		MSPS
			DVDD = 3 V to 3.6 V	67
t	Output settling time to 0.1%²			35		ns
s(DAC)
tpd	Output propagation delay			1		ns
GE	Glitch energy³		Worst case LSB transition (code 127 ± code 128)	5		pV±s
t	Output rise time 10% to 90%²			1		ns
r(IOUT)
t	Output fall time 90% to 10%²			1		ns
f(IOUT)
	Output noise		IOUTFS = 20 mA	15
						pA/√ HZ
			IOUTFS = 2 mA	10
AC linearity (to Nyquist)
			fCLK = 5 MSPS, fOUT = 1 MHz, TA = 25°C	50
			fCLK = 25 MSPS, fOUT = 1 MHz, TA = 25°C	50
			fCLK = 25 MSPS, fOUT = 5 MHz, TA = 25°C	50
			fCLK = 25 MSPS, fOUT = 10 MHz, TA = 25°C	48
			fCLK = 50 MSPS, fOUT = 1 MHz, TA = 25°C	50
			fCLK = 50 MSPS, fOUT = 5 MHz, TA = 25°C	50
SINAD	Signal-to-noise and distortion ratio		fCLK = 50 MSPS, fOUT = 20 MHz, TA = 25°C	47		dB
			fCLK = 70 MSPS, fOUT = 5 MHz, TA = 25°C	50
			fCLK = 70 MSPS, fOUT = 10 MHz, TA = 25°C	50
			fCLK = 70 MSPS, fOUT = 20 MHz, TA = 25°C	46
			fCLK = 100 MSPS, fOUT = 10 MHz, TA = 25°C	47
			fCLK = 100 MSPS, fOUT = 22 MHz, TA = 25°C	47
			fCLK = 100 MSPS, fOUT = 40 MHz, TA = 25°C	45
			fCLK = 5 MSPS, fOUT = 1 MHz, TA = 25°C	±69
			fCLK = 25 MSPS, fOUT = 1 MHz, TA = 25°C	±67
			fCLK = 25 MSPS, fOUT = 5 MHz, TA = 25°C	±69
			fCLK = 25 MSPS, fOUT = 10 MHz, TA = 25°C	±57
			fCLK = 50 MSPS, fOUT = 1 MHz, TA = 25°C	±67
			fCLK = 50 MSPS, fOUT = 1 MHz, TA = ±40°C to 85°C	±64
THD	Total harmonic distortion		fCLK = 50 MSPS, fOUT = 5 MHz, TA = 25°C	±66		dBc
			fCLK = 50 MSPS, fOUT = 20 MHz, TA = 25°C	±52
			fCLK = 70 MSPS, fOUT = 5 MHz, TA = 25°C	±64
			fCLK = 70 MSPS, fOUT = 10 MHz, TA = 25°C	±60
			fCLK = 70 MSPS, fOUT = 20 MHz, TA = 25°C	±48
			fCLK = 100 MSPS, fOUT = 10 MHz, TA = 25°C	±53
			fCLK = 100 MSPS, fOUT = 22 MHz, TA = 25°C	±53
			fCLK = 100 MSPS, fOUT = 40 MHz, TA = 25°C	±47
² Measured single ended into 50 Ω load at IOUT1.
³ Single-ended output IOUT1, 50 Ω doubly terminated load.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

5

THS5641A

8-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS277 ±MARCH 2000

electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA, single-ended output IOUT1, 50 Ω doubly terminated load (unless otherwise noted) (continued)

ac specifications

PARAMETER	TEST CONDITIONS	MIN TYP MAX	UNIT
AC linearity (to Nyquist)
	fCLK = 5 MSPS, fOUT = 1 MHz, TA = 25°C	68
	fCLK = 25 MSPS, fOUT = 1 MHz, TA = 25°C	69
	fCLK = 25 MSPS, fOUT = 5 MHz, TA = 25°C	68
	fCLK = 25 MSPS, fOUT = 10 MHz, TA = 25°C	56
	fCLK = 50 MSPS, fOUT = 1 MHz, TA = 25°C	67
	fCLK = 50 MSPS, fOUT = 5 MHz, TA = 25°C	67
SFDR Spurious free dynamic range	fCLK = 50 MSPS, fOUT = 20 MHz, TA = 25°C	53	dBc
	fCLK = 70 MSPS, fOUT = 5 MHz, TA = 25°C	65
	fCLK = 70 MSPS, fOUT = 10 MHz, TA = 25°C	63
	fCLK = 70 MSPS, fOUT = 20 MHz, TA = 25°C	48
	fCLK = 100 MSPS, fOUT = 10 MHz, TA = 25°C	55
	fCLK = 100 MSPS, fOUT = 22 MHz, TA = 25°C	55
	fCLK = 100 MSPS, fOUT = 40 MHz, TA = 25°C	48

digital specifications

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Interface
VIH	High-level input voltage	DVDD = 5 V	3.5	5		V
		DVDD = 3.3 V	2.1	3.3
VIL	Low-level input voltage	DVDD = 5 V		0	1.3	V
		DVDD = 3.3 V		0	0.9
IIH	High-level input current	DVDD = 3 V to 5.5 V	±10		10	A
IIL	Low-level input current	DVDD = 3 V to 5.5 V	±10		10	A
	Input capacitance		1		5	pF
Timing
tsu(D)	Input setup time		1			ns
th(D)	Input hold time		1			ns
tw(LPH)	Input latch pulse high time		4			ns
td(D)	Digital delay time				1	clk

Specifications subject to change

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

THS5641A 8-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS277 ±MARCH 2000

TYPICAL CHARACTERISTICS²

SPURIOUS FREE DYNAMIC RANGE vs

OUTPUT FREQUENCY

78

Fclock = 5 MSPS

	72				AVDD = 5 V
					DVDD = 5 V
	66		Fclock = 25 MSPS
± dBc				Fclock = 50 MSPS
	60
SFDR				Fclock = 70 MSPS
	54			Fclock = 100 MSPS
	48
	42
	0	10	20	30	40	50
			Fout ± MHz

Figure 1

SIGNAL-TO-NOISE AND DISTORTION RATIO vs

OUTPUT FREQUENCY

	54
		5 MSPS
	51				AVDD = 5 V
					DVDD = 5 V
			25 MSPS
dB			50 MSPS
±	48
SINAD
					100 MSPS
	45
			70 MSPS
	42
	0	10	20	30	40	50
			Fout ± MHz

Figure 3

TOTAL HARMONIC DISTORTION

				vs
			OUTPUT FREQUENCY
	±42
		70 MSPS		100 MSPS
	±48
	±54
dBc			50 MSPS
	±60
±			25 MSPS
THD
	±66
	±72				AVDD = 5 V
					DVDD = 5 V
		5 MSPS
	±78
	0	10	20	30	40	50
			Fout ± MHz

Figure 2

SPURIOUS FREE DYNAMIC RANGE

				vs
			OUTPUT FREQUENCY
	78
	72	5 MSPS				AVDD = 3.3 V
						DVDD = 3.3 V
			25 MSPS
dBc	66			50 MSPS
SFDR ±	60
	54					67 MSPS
	48
	0	5	10	15	20	25	30	35
				Fout ± MHz

Figure 4

²AVDD and DVDD specified for each chart seperately, IOUTFS = 20 mA, single-ended output IOUT1, 50 Ω doubly terminated load, TA = 25°C (unless otherwise noted.)

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

7

THS5641A

8-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS277 ±MARCH 2000

TYPICAL CHARACTERISTICS²

TOTAL HARMONIC DISTORTION

				vs
			OUTPUT FREQUENCY
	±48
	±54					67 MSPS
		5 MSPS			50 MSPS
	±60
dBc								± dB
THD ±	±66							SINAD
			25 MSPS
	±72					AVDD = 3.3 V
						DVDD = 3.3 V
	±78
	0	5	10	15	20	25	30	35
				Fout ± MHz

Figure 5

SIGNAL-TO-NOISE AND DISTORTION RATIO vs

OUTPUT FREQUENCY

54
					AVDD = 3.3 V
					DVDD = 3.3 V
51
		25 MSPS
				50 MSPS
48
	5 MSPS				67 MSPS
45
42
0	5	10	15	20	25	30	35

Fout ± MHz

Figure 6

SINAD ± dB

SIGNAL-TO-NOISE AND DISTORTION RATIO vs

TEMPERATURE AT 70 MSPS

54

51		Fout	= 2 MHZ

Fout = 10 MHZ

48

Fout = 25 MHZ

45

AVDD = 5 V

DVDD = 5 V

42
±40		±20	0	20	40	60	80
			Ambient Temperature ± °C

Figure 7

SIGNAL-TO-NOISE AND DISTORTION RATIO vs

TEMPERATURE AT 70 MSPS

	54
	51			Fout = 2 MHz
± dB	48
SINAD				Fout = 10 MHz
	45			Fout = 25 MHz
					AVDD = 3.3 V
					DVDD = 3.3 V
	42
	±40	±20	0	20	40	60	80
			Ambient Temperature ± °C

Figure 8

²AVDD and DVDD specified for each chart seperately, IOUTFS = 20 mA, single-ended output IOUT1, 50 Ω doubly terminated load, TA = 25°C (unless otherwise noted.)

8	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

THS5641A 8-BIT, 100 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS277 ±MARCH 2000

TYPICAL CHARACTERISTICS²

SPURIOUS FREE DYNAMIC RANGE vs

FULL-SCALE OUTPUT CURRENT AT 100 MSPS

	78
	72
	66			Fout = 2.5 MHz
± dBc	60			Fout = 10 MHz
SFDR	54			Fout = 28.6 MHz
	48
				Fout = 40 MHz
	42							AVDD = 5 V
								DVDD = 5 V
	36
	2	4	6	8	10	12	14	16	18	20
					IoutFS ± mA

Figure 9

SPURIOUS FREE DYNAMIC RANGE vs

OUTPUT FREQUENCY AT 50 MSPS

	78
	72				AVDD = 5 V
					DVDD = 5 V
dBc	66
			DIFFERENTIAL OUTPUT
±
SFDR	60
	54		SINGLE-ENDED
			OUTPUT IOUT1
	48
	0	5	10	15	20	25

Fout ± MHz

Figure 11

SIGNAL-TO-NOISE AND DISTORTION RATIO vs

FULL-SCALE OUTPUT CURRENT AT 100 MSPS

	54
		Fout = 2.5 MHz
	48	Fout = 10 MHz
± dB	42	Fout = 28.6 MHz
SINAD
		Fout = 40 MHz
	36
		AVDD = 5 V
		DVDD = 5 V

30

2	4	6	8	10	12	14	16	18	20
				IoutFS ± mA

Figure 10

SIGNAL-TO-NOISE AND DISTORTION RATIO vs

OUTPUT FREQUENCY AT 50 MSPS

	54
					AVDD = 5 V
					DVDD = 5 V
	51
				DIFFERENTIAL OUTPUT
dB		SINGLE-ENDED
±	48	OUTPUT IOUT1
SINAD
	45
	42
	0	5	10	15	20	25

Fout ± MHz

Figure 12

²AVDD and DVDD specified for each chart seperately, IOUTFS = 20 mA, single-ended output IOUT1, 50 Ω doubly terminated load, TA = 25°C (unless otherwise noted.)

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

9