ANALOG DEVICES AD633 Service Manual

Data Sheet

FEATURES

4-quadrant multiplication

Low cost, 8-lead SOIC and PDIP packages Complete—no external components required Laser-trimmed accuracy and stability

Total error within 2% of full scale Differential high impedance X and Y inputs High impedance unity-gain summing input Laser-trimmed 10 V scaling reference

APPLICATIONS

Multiplication, division, squaring Modulation/demodulation, phase detection Voltage-controlled amplifiers/attenuators/filters

GENERAL DESCRIPTION

The AD633 is a functionally complete, four-quadrant, analog multiplier. It includes high impedance, differential X and Y inputs, and a high impedance summing input (Z). The low impedance output voltage is a nominal 10 V full scale provided by a buried Zener. The AD633 is the first product to offer these features in modestly priced 8-lead PDIP and SOIC packages.

The AD633 is laser calibrated to a guaranteed total accuracy of 2% of full scale. Nonlinearity for the Y input is typically less than 0.1% and noise referred to the output is typically less than 100 μV rms in a 10 Hz to 10 kHz bandwidth. A 1 MHz bandwidth, 20 V/μs slew rate, and the ability to drive capacitive loads make the AD633 useful in a wide variety of applications where simplicity and cost are key concerns.

The versatility of the AD633 is not compromised by its simplicity. The Z input provides access to the output buffer amplifier, enabling the user to sum the outputs of two or more multipliers, increase the multiplier gain, convert the output voltage to a current, and configure a variety of applications.

Rev. I

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Low Cost

Analog Multiplier

AD633

FUNCTIONAL BLOCK DIAGRAM

	X1
	1
	X2
	A	W
	1
	10V	Z
	Y1
	1	023-
	Y2
		00786

Figure 1.

The AD633 is available in 8-lead PDIP and SOIC packages. It is specified to operate over the 0°C to 70°C commercial temperature range (J Grade) or the −40°C to +85°C industrial temperature range (A Grade).

PRODUCT HIGHLIGHTS

1.The AD633 is a complete four-quadrant multiplier offered in low cost 8-lead SOIC and PDIP packages. The result is a product that is cost effective and easy to apply.

2.No external components or expensive user calibration are required to apply the AD633.

3.Monolithic construction and laser calibration make the device stable and reliable.

4.High (10 MΩ) input resistances make signal source loading negligible.

5.Power supply voltages can range from ±8 V to ±18 V. The internal scaling voltage is generated by a stable Zener diode; multiplier accuracy is essentially supply insensitive.

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AD633	Data Sheet

TABLE OF CONTENTS
Features ..............................................................................................	1
Applications.......................................................................................	1
Functional Block Diagram ..............................................................	1
General Description .........................................................................	1
Product Highlights ...........................................................................	1
Revision History ...............................................................................	2
Specifications.....................................................................................	3
Absolute Maximum Ratings............................................................	4
Thermal Resistance ......................................................................	4
ESD Caution..................................................................................	4
Pin Configurations and Function Descriptions ...........................	5
Typical Performance Characteristics .............................................	6
Functional Description ....................................................................	7
Error Sources.................................................................................	7
REVISION HISTORY
2/12—Rev. H to Rev. I
Changes to Figure 1..........................................................................	1
Changes to Figure 2..........................................................................	5
Changes to Generating Inverse Functions Section ......................	8
Changes to Figure 15........................................................................	9
Added Evaluation Board Section and Figure 23 to Figure 29,
Renumbered Sequentially..............................................................	12
Changes to Ordering Guide ..........................................................	15
4/11—Rev. G to Rev. H
Changes to Figure 1, Deleted Figure 2...........................................	1
Added Figure 2, Figure 3, Table 4, Table 5 ....................................	5
Deleted Figure 9, Renumbered Subsequent Figures ....................	6
Changes to Figure 15........................................................................	9

Applications Information .................................................................	8
Multiplier Connections ................................................................	8
Squaring and Frequency Doubling.............................................	8
Generating Inverse Functions .....................................................	8
Variable Scale Factor.....................................................................	9
Current Output..............................................................................	9
Linear Amplitude Modulator ......................................................	9
Voltage-Controlled, Low-Pass and High-Pass Filters...............	9
Voltage-Controlled Quadrature Oscillator...................................	10
Automatic Gain Control (AGC) Amplifiers...........................	10
Outline Dimensions .......................................................................	14
Ordering Guide ..........................................................................	15

4/10—Rev. F to Rev. G
Changes to Equation 1......................................................................	6
Changes to Equation 5 and Figure 14.............................................	7
Changes to Figure 21.........................................................................	9
10/09—Rev. E to Rev. F
Changes to Format .............................................................	Universal
Changes to Figure 21.........................................................................	9
Updated Outline Dimensions.......................................................	11
Changes to Ordering Guide ..........................................................	12
10/02—Rev. D to Rev. E
Edits to Title of 8-Lead Plastic SOIC Package (RN-8) .................	1
Edits to Ordering Guide ...................................................................	2
Change to Figure 13 ..........................................................................	7
Updated Outline Dimensions..........................................................	8

Rev. I | Page 2 of 16

Data Sheet						AD633
SPECIFICATIONS
TA = 25°C, VS = ±15 V, RL ≥ 2 kΩ.
Table 1.
			AD633J, AD633A
Parameter	Conditions	Min	Typ		Max	Unit
TRANSFER FUNCTION		W =	(X1 − X2)(Y1 −Y2)		+ Z
			10 V
MULTIPLIER PERFORMANCE
Total Error	−10 V ≤ X, Y ≤ +10 V		±1		±21	% full scale
TMIN to TMAX			±3			% full scale
Scale Voltage Error	SF = 10.00 V nominal		±0.25%			% full scale
Supply Rejection	VS = ±14 V to ±16 V		±0.01			% full scale
Nonlinearity, X	X = ±10 V, Y = +10 V		±0.4		±11	% full scale
Nonlinearity, Y	Y = ±10 V, X = +10 V		±0.1		±0.41	% full scale
X Feedthrough	Y nulled, X = ±10 V		±0.3		±11	% full scale
Y Feedthrough	X nulled, Y = ±10 V		±0.1		±0.41	% full scale
Output Offset Voltage			±5		±501	mV
DYNAMICS
Small Signal Bandwidth	VO = 0.1 V rms		1			MHz
Slew Rate	VO = 20 V p-p		20			V/µs
Settling Time to 1%	ΔVO = 20 V		2			µs
OUTPUT NOISE
Spectral Density			0.8			µV/√Hz
Wideband Noise	f = 10 Hz to 5 MHz		1			mV rms
	f = 10 Hz to 10 kHz		90			µV rms
OUTPUT
Output Voltage Swing		±111				V
Short Circuit Current	RL = 0 Ω		30		401	mA
INPUT AMPLIFIERS
Signal Voltage Range	Differential	±101				V
	Common mode	±101				V
Offset Voltage (X, Y)			±5		±301	mV
CMRR (X, Y)	VCM = ±10 V, f = 50 Hz	601	80			dB
Bias Current (X, Y, Z)			0.8		2.01	µA
Differential Resistance			10			MΩ
POWER SUPPLY
Supply Voltage
Rated Performance			±15			V
Operating Range		±81			±181	V
Supply Current	Quiescent		4		61	mA

1This specification was tested on all production units at electrical test. Results from those tests are used to calculate outgoing quality levels. All minimum and maximum specifications are guaranteed; however, only this specification was tested on all production units.

Rev. I | Page 3 of 16

AD633

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter	Rating
Supply Voltage	±18 V
Internal Power Dissipation	500 mW
Input Voltages1	±18 V
Output Short-Circuit Duration	Indefinite
Storage Temperature Range	−65°C to +150°C
Operating Temperature Range
AD633J	0°C to 70°C
AD633A	−40°C to +85°C
Lead Temperature (Soldering, 60 sec)	300°C
ESD Rating	1000 V

1For supply voltages less than ±18 V, the absolute maximum input voltage is equal to the supply voltage.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 3.

Package Type	θJA	Unit
8-Lead PDIP	90	°C/W
8-Lead SOIC	155	°C/W

ESD CAUTION

Rev. I | Page 4 of 16

Data Sheet

AD633

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

X1		1																				8	+VS	Y1	1														1
			1																								1
																								Y2
X2		2										A								7			W		2				1
			1																										10V
Y1		3	10V																		6		Z	–VS	3											A
			1
Y2		4																		5			–VS	Z	4
			AD633JN/AD633AN																										AD633JR/AD633AR
			W =		(X1 – X2)(Y1 – Y2)									+ Z									-001						W =		(X1 – X2)(Y1 – Y2)								+ Z
																							00786
									10V																									10V
				Figure 2. 8-Lead PDIP																									Figure 3. 8-Lead SOIC

8 X2

7 X1

6 +VS

5 W

00786-002

Table 4. 8-Lead PDIP Pin Function Descriptions

Pin No.	Mnemonic	Description
1	X1	X Multiplicand Noninverting Input
2	X2	X Multiplicand Inverting Input
3	Y1	Y Multiplicand Noninverting Input
4	Y2	Y Multiplicand Inverting Input
5	−VS	Negative Supply Rail
6	Z	Summing Input
7	W	Product Output
8	+VS	Positive Supply Rail

Table 5. 8-Lead SOIC Pin Function Descriptions

Pin No.	Mnemonic	Description
1	Y1	Y Multiplicand Noninverting Input
2	Y2	Y Multiplicand Inverting Input
3	−VS	Negative Supply Rail
4	Z	Summing Input
5	W	Product Output
6	+VS	Positive Supply Rail
7	X1	X Multiplicand Noninverting Input
8	X2	X Multiplicand Inverting Input

Rev. I | Page 5 of 16