Texas Instruments UC3848N, UC3848DWTR, UC3848DW, UC2848DW, UC2848N Datasheet
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UC1848
UC2848
UC3848
Average Current Mode PWM Controller
FEATURES
∙Practical Primary Side Control of Isolated Power Supplies with DC Control of Secondary Side Current
∙Accurate Programmable Maximum Duty Cycle Clamp
∙Maximum Volt-Second Product Clamp to Prevent Core Saturation
∙Practical Operation Up to 1MHz
∙High Current (2A Pk) Totem Pole Output Driver
∙Wide Bandwidth (8MHz) Current Error Amplifier
∙Under Voltage Lockout Monitors VCC, VIN and VREF
∙Output Active Low During UVLO
∙Low Startup Current (500μA)
∙Precision 5V Reference (1%)
DESCRIPTION
BLOCK DIAGRAM
UDG-93003-1 |
The UC3848 family of PWM control ICs makes primary |
output driver. The current error amplifier easily interfaces |
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side average current mode control practical for isolated |
with an optoisolator from a secondary side voltage sens- |
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switching converters. Average current mode control in- |
ing circuit. |
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sures that both cycle by cycle peak switch current and |
A full featured undervoltage lockout (UVLO) circuit is con- |
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maximum average inductor current are well defined and |
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tained in the UC3848. UVLO monitors the supply voltage |
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will not run away in a short circuit situation. The UC3848 |
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to the controller (VCC), the reference voltage (VREF), |
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can be used to control a wide variety of converter topolo- |
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and the input line voltage (VIN). All three must be good |
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gies. |
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before soft start commences. If either VCC or VIN is low, |
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In addition to the basic functions required for pulse width |
the supply current required by the chip is only 500μA and |
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modulation, the UC3848 implements a patented tech- |
the output is actively held low. |
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nique of sensing secondary current in an isolated buck |
Two on board protection features set controlled limits to |
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derived converter from the primary side. A current wave- |
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prevent transformer core saturation. Input voltage is mon- |
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form synthesizer monitors switch current and simulates |
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itored and pulse width is constrained to limit the maxi- |
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the inductor current down slope so that the complete cur- |
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mum volt-second product applied to the transformer. A |
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rent waveform can be constructed on the primary side |
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unique patented technique limits maximum duty cycle |
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without actual secondary side measurement. This infor- |
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within 3% of a user programmed value. |
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mation on the primary side allows for full DC control of |
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These two features allow for more optimal use of trans- |
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output current. |
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The UC3848 circuitry includes a precision reference, a |
formers and switches, resulting in reduced system size |
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and cost. |
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wide bandwidth error amplifier for average current con- |
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Patents embodied in the UC3848 belong to Lambda |
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trol, an oscillator to generate the system clock, latching |
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PWM comparator and logic circuits, and a high current |
Electronics Incorporated and are licensed for use in ap- |
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plications employing these devices. |
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4/96 |
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Pin 15). . . . . . . . . . . . . . . . . . . . . . . . . . . . 22V Output Current, Source or Sink (Pin 14)
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A Pulse (0.5
s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2A Power Ground to Ground (Pin 1 to Pin 13) . . . . . . . . . . . ± 0.2V
Analog Input Voltages
(Pins 3, 4, 7, 8, 12, 16) . . . . . . . . . . . . . . . . . . . . . –0.3 to 7V Analog Input Currents, Source or Sink
(Pins 3, 4, 7, 8, 11, 12, 16) . . . . . . . . . . . . . . . . . . . . . . 1mA
UC1848
UC2848
UC3848
Analog Output Currents, Source or Sink (Pins 5 & 10) . . . 5mA Power Dissipation at TA = 60°C . . . . . . . . . . . . . . . . . . . . . . 1W Storage Temperature Range . . . . . . . . . . . . . . . −65°C to +150 °C Lead Temperature (Soldering 10 seconds) . . . . . . . . . . +300°C
Notes: All voltages are with respect to ground (DIL and SOIC Pin 1). Currents are positive into the specified terminal. Pin numbers refer to the 16 pin DIL and SOIC packages. Consult Packaging Section of Databook for thermal limitations and considerations of packages.
CONNECTION DIAGRAMS
DIL-16, SOIC-16 (Top View) |
PLCC-20 & LCC-20 |
PACKAGE PIN FUNCTION |
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J, N, or DW Packages |
(Top View) |
FUNCTION |
PIN |
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N/C |
1 |
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Q & L Packages |
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GND |
2 |
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VREF |
3 |
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NI |
4 |
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INV |
5 |
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N/C |
6 |
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CAO |
7 |
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CT |
8 |
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VS |
9 |
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DMAX |
10 |
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N/C |
11 |
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CDC |
12 |
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CI |
13 |
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IOFF |
14 |
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ION |
15 |
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N/C |
16 |
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PGND |
17 |
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OUT |
18 |
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VCC |
19 |
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UV |
20 |
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, all specifications are over the junction temperature range of −55°C to +125°C for the UC1848, −40°C to +85°C for the UC2848, and 0°C to +70°C for the UC3848. Test conditions are: VCC = 12V, CT = 400pF, CI = 100pF, IOFF = 100μA, CDC = 100nF, Cvs = 100pF, and Ivs = 400μA, TA = TJ.
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNITS |
Real Time Current Waveform Synthesizer |
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Ion Amplifier |
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Offset Voltage |
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0.95 |
1 |
1.05 |
V |
Slew Rate (Note 1) |
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20 |
25 |
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V/μs |
lib |
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-2 |
-20 |
μA |
IOFF Current Mirror |
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Input Voltage |
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0.95 |
1 |
1.05 |
V |
Current Gain |
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0.9 |
1 |
1.1 |
A/A |
Current Error Amplifier |
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AVOL |
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60 |
100 |
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dB |
Vio |
12V ≤ VCC 20V, 0V VCM 5V |
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10 |
mV |
lib |
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-0.5 |
-3 |
μA |
Voh |
IO = −200μA |
3 |
3.3 |
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V |
Vol |
IO = 200μA |
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0.3 |
0.6 |
V |
Source Current |
VO = 1V |
1.4 |
1.6 |
2.0 |
mA |
GBW Product |
f = 200kHz |
5 |
8 |
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MHz |
Slew Rate (Note 1) |
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8 |
10 |
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V/μs |
2
UC1848
UC2848
UC3848
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, all specifications are over the junction temperature range of −55°C to +125°C for the UC1848, −40°C to +85°C for the UC2848, and 0°C to +70°C for the UC3848. Test conditions are: VCC = 12V, CT = 400pF, CI = 100pF, IOFF = 100μA, CDC = 100nF, Cvs = 100pF, and Ivs = 400μA, TA = TJ.
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNITS |
Oscillator |
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Frequency |
TA = 25°C |
240 |
250 |
260 |
kHz |
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235 |
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265 |
kHz |
Ramp Amplitude |
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1.5 |
1.65 |
1.8 |
V |
Duty Cycle Clamp |
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Max Duty Cycle |
V(DMAX) = 0.75 ∙ VREF |
73.5 |
76.5 |
79.5 |
% |
Volt Second Clamp |
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Max On Time |
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900 |
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1100 |
ns |
VCC Comparator |
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Turn-on Threshold |
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13 |
14 |
V |
Turn-off Threshold |
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9 |
10 |
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V |
Hysteresis |
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2.5 |
3 |
3.5 |
V |
UV Comparator |
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Turn-on Threshold |
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4.1 |
4.35 |
4.6 |
V |
RHYSTERESIS |
Vuv = 4.2V |
77 |
90 |
103 |
kΩ |
Reference |
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VREF |
TA = 25°C |
4.95 |
5 |
5.05 |
V |
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0 < IO < 10mA, 12 < VCC < 20 |
4.93 |
|
5.07 |
V |
Line Regulation |
12 < VCC < 20V |
|
4 |
15 |
mV |
Load Regulation |
0 < IO < 10mA |
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3 |
15 |
mV |
Short Circuit Current |
VREF = 0V |
30 |
50 |
70 |
mA |
Output Stage |
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Rise & Fall Time (Note 1) |
Cl = 1nF |
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20 |
45 |
ns |
Output Low Saturation |
IO = 20mA |
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0.25 |
0.4 |
V |
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IO = 200mA |
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1.2 |
2.2 |
V |
Output High Saturation |
IO = -200mA |
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2.0 |
3.0 |
V |
UVLO Output Low Saturation |
IO = 20mA |
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0.8 |
1.2 |
V |
ICC |
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ISTART |
VCC = 12V |
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0.2 |
0.4 |
mA |
ICC (pre-start) |
VCC = 15V, V(UV) = 0 |
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0.5 |
1 |
mA |
ICC (run) |
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22 |
26 |
mA |
Note 1: Guaranteed by design.
APPLICATION INFORMATION
Under Voltage Lockout
The Under Voltage Lockout block diagram is shown in Fig 1. The VCC comparator monitors chip supply voltage. Hysteretic thresholds are set at 13V and 10V to facilitate off-line applications. If the VCC comparator is low, ICC is low (<500μA) and the output is low.
The UV comparator monitors input line voltage (VIN). A pair of resistors divides the input line to UV. Hysteretic in-
put line thresholds are programmed by Rv1 and Rv2. The thresholds are
VIN(on) = 4.35V ∙ (1 + Rv1/Rv2′) and VIN(off) = 4.35V ∙ (1 + Rv1/Rv2) where Rv2′= Rv2||90k.
The resulting hysteresis is VIN(hys) = 4.35V ∙ Rv1 / 90k.
When the UV comparator is low, ICC is low (500μA) and the output is low.
3
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