Texas Instruments CD74HCT109M96, CD74HCT109M, CD74HCT109E, CD74HC109M96, CD74HC109M Datasheet

Data sheet acquired from Harris Semiconductor SCHS140

March 1998

CD74HC109,

CD74HCT109

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features

at VCC = 5V

•

Asynchronous Set and Reset

• HCT Types

- 4.5V to 5.5V Operation

[ /Title

•

Schmitt Trigger Clock Inputs

- Direct LSTTL Input Logic Compatibility,

(CD74H

•

Typical Propagation Delay = 18ns at VCC = 5V,

VIL= 0.8V (Max), VIH = 2V (Min)

C109,

CL = 15pF, TA = 25oC

- CMOS Input Compatibility, I ≤ 1 A at V

, V

CD74H

l

OL

OH

•

Typical fMAX = 60MHz at VCC = 5V, CL = 15pF,

Description

CT109)

TA = 25oC

/Subject

•

Fanout (Over Temperature Range)

The Harris CD74HC109 and CD74HCT109 are dual J-

flip-

K

(Dual J-

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

flops with set and reset. The flip-flop changes state with the

K Flip-

-

Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

positive transition of Clock (1CP and 2CP).

Flop

The flip-flop is set and reset by active-low

and

•

Wide Operating Temperature Range . . . -55oC to 125oC

S

R,

with Set

•

Balanced Propagation Delay and Transition Times

respectively. A low

on both the

set and reset inputs

simultaneously will force both Q and Q outputs high.

and

•

Significant Power Reduction Compared to LSTTL

However, both set

and reset going high simultaneously

Reset

results in an unpredictable output condition.

Logic ICs

• HC Types

Ordering Information

-

2V to 6V Operation

TEMP. RANGE

PKG.

-

High Noise Immunity: NIL = 30%, NIH = 30% of VCC

PART NUMBER

(oC)

PACKAGE

NO.

Pinout

CD74HC109, CD74HCT109

(PDIP, SOIC)

TOP VIEW

1R

1

16 VCC

1J

2

15

2R

1K

3

14

2J

1CP

4

13 2K

1S

5

12 2CP

1Q

6

11

2S

1Q

7

10

2Q

GND

8

9

2Q

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.	File Number 1667.1

Copyright © Harris Corporation 1998

1

CD74HC109, CD74HCT109

Functional Diagram

1S	5
1J	2		6
			1Q
1K	3	F/F 1	7
	4		1Q
1CP
	1
1R
2S	11
2J	14		10
			2Q
2K	13	F/F 2	9
	12		2Q
2CP
2R	15		GND = 8
			VCC = 16

TRUTH TABLE

INPUTS

OUTPUTS

CP

J

Q

S

R

K

Q

L

H

X

X

X

H

L

H

L

X

X

X

L

H

L

L

X

X

X

H (Note 3)

H (Note 3)

H

H

↑

L

L

L

H

H

H

↑

H

L

Toggle

H

H

↑

L

H

No Change

H

H

↑

H

H

H

L

H

H

L

X

X

No Change

NOTES:

H= High Level (Steady State)

L= Low Level (Steady State)

X= Don’t Care

↑= Low-to-High Transition

3. Unpredictable and unstable condition if both S and R go high simultaneously.

Logic Diagram

5(11)
S
2(14)		S			6(10)
J	J			Q	Q
3(13)			FF		7(9)
K	K CL		CL	R Q	Q
4(12)
CP
1(15)
R
16
VCC
8
GND

2

CD74HC109, CD74HCT109

Absolute Maximum Ratings

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . .	-0.5V to 7V
DC Input Diode Current, IIK	±20mA
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . .
DC Drain Current, per Output, IO	±25mA
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .
DC Output Diode Current, IOK	±20mA
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . .
DC Output Source or Sink Current per Output Pin, IO	±25mA
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . .
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . .	. . . .±50mA

Thermal Information
Thermal Resistance (Typical, Note 4)	θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	.	90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	.	160
Maximum Junction Temperature (Hermetic Package or Die) . .		. 175oC
Maximum Junction Temperature (Plastic Package) .	. . . . . .	. 150oC
Maximum Storage Temperature Range . . . . . . . . . .	-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . .	. . . . . .	. 300oC
(SOIC - Lead Tips Only)

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC CP Input Rise and Fall Time, tr, tf

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max) Input Rise and Fall Time (All Inputs Except CP), tr, tf

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

4. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

		TEST				25oC		-40oC TO 85oC		-55oC TO 125oC
		CONDITIONS
PARAMETER	SYMBOL	VI (V)	IO (mA)	VCC (V)	MIN	TYP	MAX	MIN	MAX	MIN	MAX	UNITS
HC TYPES
High Level Input	VIH	-	-	2	1.5	-	-	1.5	-	1.5	-	V
Voltage
				4.5	3.15	-	-	3.15	-	3.15	-	V
				6	4.2	-	-	4.2	-	4.2	-	V
Low Level Input	VIL	-	-	2	-	-	0.5	-	0.5	-	0.5	V
Voltage
				4.5	-	-	1.35	-	1.35	-	1.35	V
				6	-	-	1.8	-	1.8	-	1.8	V
High Level Output	VOH	VIH or	-0.02	2	1.9	-	-	1.9	-	1.9	-	V
Voltage		VIL
				4.5	4.4	-	-	4.4	-	4.4	-	V
CMOS Loads
				6	5.9	-	-	5.9	-	5.9	-	V
High Level Output			-	-	-	-	-	-	-	-	-	V
Voltage
			-4	4.5	3.96	-	-	3.84	-	3.7	-	V
TTL Loads
			-5.2	6	5.48	-	-	5.34	-	5.2	-	V

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