Motorola MC74HC162D, MC74HC162N, MC74HC160D, MC74HC160N, MC54HC160J Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Presettable Counters

High±Performance Silicon±Gate CMOS

The MC54/74HC160 and HC162 are identical in pinout to the LS160 and LS162, respectively. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

The HC160 and HC162 are programmable BCD counters with asynchronous and synchronous Reset inputs, respectively.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2 to 6 V

•Low Input Current: 1 μA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 234 FETs or 58.5 Equivalent Gates

LOGIC DIAGRAM

			P0	3	14	Q0
PRESENT			P1	4	13	Q1	BCD OR
	DATA		P2	5	12		BINARY
INPUTS						Q2	OUTPUTS
			P3	6	11	Q3
				2	15	RIPPLE
		CLOCK				CARRY
						OUT
		RESET
			LOAD
COUNT		ENABLE P				PIN 16 = VCC
ENABLES
		ENABLE T				PIN 8 = GND

MC54/74HC160

MC54/74HC162

		J SUFFIX
16	CERAMIC PACKAGE
		CASE 620±10
	1
		N SUFFIX
16	PLASTIC PACKAGE
		CASE 648±08
	1
		D SUFFIX
16		SOIC PACKAGE
	1	CASE 751B±05
	ORDERING INFORMATION
	MC54HCXXXJ	Ceramic
	MC74HCXXXN	Plastic
	MC74HCXXXD	SOIC

PIN ASSIGNMENT

RESET		1	16		VCC
CLOCK		2	15		RIPPLE
					CARRY OUT
P0		3	14		Q0
		4	13		Q1
P1
P2		5	12		Q2
P3		6	11		Q3
ENABLE P		7	10		ENABLE T
GND		8	9		LOAD

	Count
Device	Mode	Reset Mode
HC160	BCD	Asynchronous
HC162	BCD	Synchronous

FUNCTION TABLE

				Inputs			Output
Clock			Reset*	Load	Enable P	Enable T	Q
			L	X	X	X	Reset
			H	L	X	X	Load Preset Data
			H	H	H	H	Count
			H	H	L	X	No Count
			H	H	X	L	No Count

* HC162 only. HC160 is an Asynchronous Reset Device H = high level

L = low level X = don't care

10/95

Motorola, Inc. 1995

REV 6

MC54/74HC160 MC54/74HC162

MAXIMUM RATINGS*

Symbol	Parameter	Value	Unit
VCC	DC Supply Voltage (Referenced to GND)	± 0.5 to + 7.0	V
Vin	DC Input Voltage (Referenced to GND)	± 1.5 to VCC + 1.5	V
Vout	DC Output Voltage (Referenced to GND)	± 0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin	± 20	mA
Iout	DC Output Current, per Pin	± 25	mA
ICC	DC Supply Current, VCC and GND Pins	± 50	mA
PD	Power Dissipation in Still Air, Plastic or Ceramic DIP²	750	mW
	SOIC Package²	500
Tstg	Storage Temperature	± 65 to + 150	_C
TL	Lead Temperature, 1 mm from Case for 10 Seconds	260	_C
	(Plastic DIP or SOIC Package)
	(Ceramic DIP)	300

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C Ceramic DIP: ± 10 mW/_C from 100_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)		0	VCC	V
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time	VCC = 2.0 V	0	1000	ns
	(Figure 1)	VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

					Guaranteed Limit
				VCC
					± 55 to	v _	v	_
Symbol	Parameter	Test Conditions		V	_				Unit
					25 C	85 C		125 C
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V		2.0	1.5	1.5		1.5	V
	Voltage	|Iout| v 20 μA		4.5	3.15	3.15		3.15
				6.0	4.2	4.2		4.2
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V		2.0	0.3	0.3		0.3	V
	Voltage	|Iout| v 20 μA		4.5	0.9	0.9		0.9
				6.0	1.2	1.2		1.2
VOH	Minimum High±Level Output	Vin = VIH or VIL		2.0	1.9	1.9		1.9	V
	Voltage	|Iout| v 20 μA		4.5	4.4	4.4		4.4
				6.0	5.9	5.9		5.9
		Vin = VIH or VIL	|Iout| v 4.0 mA	4.5	3.98	3.84		3.70
			|Iout| v 5.2 mA	6.0	5.48	5.34		5.20
VOL	Maximum Low±Level Output	Vin = VIH or VIL		2.0	0.1	0.1		0.1	V
	Voltage	|Iout| v 20 μA		4.5	0.1	0.1		0.1
				6.0	0.1	0.1		0.1
		Vin = VIH or VIL	|Iout| v 4.0 mA	4.5	0.26	0.33		0.40
			|Iout| v 5.2 mA	6.0	0.26	0.33		0.40
Iin	Maximum Input Leakage Current	Vin = VCC or GND		6.0	± 0.1	± 1.0		± 1.0	μA
ICC	Maximum Quiescent Supply	Vin = VCC or GND		6.0	8	80		160	μA
	Current (per Package)	Iout = 0 μA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

MOTOROLA

2

MC54/74HC160 MC54/74HC162

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

			Guaranteed Limit
		VCC
			± 55 to
Symbol	Parameter	V	25_C	v 85_C	v 125_C	Unit
fmax	Maximum Clock Frequency (50% Duty Cycle)*	2.0	6.0	4.8	4.0	MHz
	(Figures 1 and 7)	4.5	30	24	20
		6.0	35	28	24
tPLH	Maximum Propagation Delay, Clock to Q	2.0	170	215	255	ns
	(Figures 1 and 7)	4.5	34	43	51
		6.0	29	37	43
tPHL		2.0	205	255	310
		4.5	41	51	62
		6.0	35	43	53
tPHL	Maximum Propagation Delay, Reset to Q (HC160 Only)	2.0	210	265	315	ns
	(Figures 2 and 7)	4.5	42	53	63
		6.0	36	45	54
tPLH	Maximum Propagation Delay, Enable T to Ripple Carry Out	2.0	160	200	240	ns
	(Figures 3 and 7)	4.5	32	40	48
		6.0	27	34	41
tPHL		2.0	195	245	295
		4.5	39	49	59
		6.0	33	42	50
tPLH	Maximum Propagation Delay, Clock to Ripple Carry Out	2.0	175	220	265	ns
	(Figures 1 and 7)	4.5	35	44	53
		6.0	30	37	45
tPHL		2.0	215	270	325
		4.5	43	54	65
		6.0	37	46	55
tPHL	Maximum Propagation Delay, Reset to Ripple Carry Out	2.0	220	275	330	ns
	(HC160 Only)	4.5	44	55	66
	(Figures 2 and 7)	6.0	37	47	56
tTLH,	Maximum Output Transition Time, Any Output	2.0	75	95	110	ns
tTHL	(Figures 1 and 7)	4.5	15	19	22
		6.0	13	16	19
Cin	Maximum Input Capacitance	Ð	10	10	10	pF

*Applies to noncascaded/nonsynchronously clocked configurations only. With synchronously cascaded counters, (1) Clock to Ripple Carry Out propagation delays, (2) Enable T or Enable P to Clock setup times, and (3) Clock to Enable T or Enable P hold times determine fmax. However,

if Ripple Carry Out of each stage is tied to the Clock of the next stage (nonsynchronously clocked), the fmax in the table above is applicable. See Applications Information in this data sheet.

NOTES:

1.

For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

2.

Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD

Power Dissipation Capacitance (Per Package)*

60

pF

* Used to determine the no±load dynamic power consumption: P

= C

PD

V

CC

2f + I

CC

V

CC

. For load considerations, see Chapter 2 of the

D

Motorola High±Speed CMOS Data Book (DL129/D).

3

MOTOROLA

MC54/74HC160 MC54/74HC162
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
			Guaranteed Limit
		VCC
			± 55 to
Symbol	Parameter	V	25_C	v 85_C	v 125_C	Unit
tsu	Minimum Setup Time, Preset Data Inputs to Clock	2.0	150	190	225	ns
	(Figure 5)	4.5	30	38	45
		6.0	26	33	38
tsu	Minimum Setup Time, Load to Clock	2.0	135	170	205	ns
	(Figure 5)	4.5	27	34	41
		6.0	23	29	35
tsu	Minimum Setup Time, Reset to Clock (HC162 only)	2.0	160	200	240	ns
	(Figure 4)	4.5	32	40	48
		6.0	27	34	41
tsu	Minimum Setup Time, Enable T or Enable P to Clock	2.0	200	250	300	ns
	(Figure 6)	4.5	40	50	60
		6.0	34	43	51
th	Minimum Hold Time, Clock to Preset Data Inputs	2.0	50	65	75	ns
	(Figure 5)	4.5	10	13	15
		6.0	9	11	13
th	Minimum Hold Time, Clock to Load	2.0	3	3	3	ns
	(Figure 5)	4.5	3	3	3
		6.0	3	3	3
th	Minimum Hold Time, Clock to Reset (HC162 only)	2.0	3	3	3	ns
	(Figure 4)	4.5	3	3	3
		6.0	3	3	3
th	Minimum Hold Time, Clock to Enable T or Enable P	2.0	3	3	3	ns
	(Figure 6)	4.5	3	3	3
		6.0	3	3	3
trec	Minimum Recovery Time, Reset Inactive to Clock (HC160 only)	2.0	125	155	190	ns
	(Figure 2)	4.5	25	31	38
		6.0	21	26	32
trec	Minimum Recovery Time, Load Inactive to Clock	2.0	125	155	190	ns
	(Figure 5)	4.5	25	31	38
		6.0	21	26	32
tw	Minimum Pulse Width, Clock	2.0	80	100	120	ns
	(Figure 1)	4.5	16	20	24
		6.0	14	17	20
tw	Minimum Pulse Width, Reset (HC160 only)	2.0	80	100	120	ns
	(Figure 2)	4.5	16	20	24
		6.0	14	17	20
tr, tf	Maximum Input Rise and Fall Times	2.0	1000	1000	1000	ns
	(Figure 1)	4.5	500	500	500
		6.0	400	400	400

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

MOTOROLA

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