MOTOROLA MC74ACT374DT, MC74ACT374ML2, MC74ACT374MR2, MC74ACT374DW, MC74ACT374DWR2 Datasheet

Octal D Type Flip Flop with 3 State Outputs

The MC74AC374/74ACT374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for busoriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops.

•Buffered Positive Edge-Triggered Clock

•3-State Outputs for Bus-Oriented Applications

•Outputs Source/Sink 24 mA

•See MC74AC273 for Reset Version

•See MC74AC377 for Clock Enable Version

•See MC74AC373 for Transparent Latch Version

•See MC74AC574 for Broadside Pinout Version

•See MC74AC564 for Broadside Pinout Version with Inverted Outputs

•′ACT374 Has TTL Compatible Inputs

VCC			O7		D7		D6		O6		O5		D5		D4		O4		CP
	20		19		18		17		16		15		14		13		12		11

MC74AC374

MC74ACT374

OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

N SUFFIX

CASE 738-03

PLASTIC

DW SUFFIX

CASE 751D-04

PLASTIC

1

2

3

4

5

6

7

8

9

10

LOGIC SYMBOL

O0

D0

D1

O1

O2

D2

D3

O3

GND

OE

PIN NAMES

D

0 D

1 D

2 D

3 D

4 D

5 D

6 D

7

D0±D7

Data Inputs

CP

OE

CP

Clock Pulse Input

OE

3-State Output Enable Input

O

0 O

1 O

2 O

3 O

4 O

5 O

6 O

7

O0±O7

3-State Outputs

TRUTH TABLE

Inputs

Outputs

Dn

CP

OE

On

H

L

H

L

L

L

X

X

H

Z

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

= LOW-to-HIGH Transition

FACT DATA

5-1

MC74AC374 MC74ACT374

FUNCTIONAL DESCRIPTION

The MC74AC374/74ACT374 consists of eight edgetriggered flip-flops with individual D-type inputs and 3-state true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold

time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.

LOGIC DIAGRAM

D0

D1

D2

D3

D4

D5

D6

D7

CP

CP

D

CP

D

CP

D

CP D

CP

D

CP

D

CP

D

CP

D

Q Q

Q Q

Q Q

Q Q

Q Q

Q Q

Q Q

Q Q

OE

O0

O1

O2

O3

O4

O5

O6

O7

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

MAXIMUM RATINGS*

Symbol	Parameter	Value	Unit
VCC	DC Supply Voltage (Referenced to GND)	±0.5 to +7.0	V
Vin	DC Input Voltage (Referenced to GND)	±0.5 to VCC +0.5	V
Vout	DC Output Voltage (Referenced to GND)	±0.5 to VCC +0.5	V
Iin	DC Input Current, per Pin	±20	mA
Iout	DC Output Sink/Source Current, per Pin	±50	mA
ICC	DC VCC or GND Current per Output Pin	±50	mA
Tstg	Storage Temperature	±65 to +150	°C

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

RECOMMENDED OPERATING CONDITIONS

	Symbol	Parameter		Min	Typ	Max	Unit
	VCC	Supply Voltage	′AC	2.0	5.0	6.0	V
			′ACT	4.5	5.0	5.5
	Vin, Vout	DC Input Voltage, Output Voltage (Ref. to GND)		0		VCC	V
		Input Rise and Fall Time (Note 1)	VCC @ 3.0 V		150
	tr, tf		VCC @ 4.5 V		40		ns/V
		′AC Devices except Schmitt Inputs
			VCC @ 5.5 V		25
	tr, tf	Input Rise and Fall Time (Note 2)	VCC @ 4.5 V		10		ns/V
		′ACT Devices except Schmitt Inputs	VCC @ 5.5 V		8.0
	TJ	Junction Temperature (PDIP)				140	°C
	TA	Operating Ambient Temperature Range		±40	25	85	°C
	IOH	Output Current Ð High				±24	mA
	IOL	Output Current Ð Low				24	mA

1.Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.

2.Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.

FACT DATA

5-2

MC74AC374 MC74ACT374

DC CHARACTERISTICS

			74AC		74AC
Symbol	Parameter	VCC	TA = +25°C		TA =	Unit		Conditions
		(V)			±40°C to +85°C
			Typ	Guaranteed Limits
VIH	Minimum High Level	3.0	1.5	2.1	2.1		VOUT = 0.1 V
	Input Voltage	4.5	2.25	3.15	3.15	V	or VCC ± 0.1 V
		5.5	2.75	3.85	3.85
VIL	Maximum Low Level	3.0	1.5	0.9	0.9		VOUT = 0.1 V
	Input Voltage	4.5	2.25	1.35	1.35	V	or VCC ± 0.1 V
		5.5	2.75	1.65	1.65
VOH	Minimum High Level	3.0	2.99	2.9	2.9		IOUT = ±50 μA
	Output Voltage	4.5	4.49	4.4	4.4	V
		5.5	5.49	5.4	5.4
							*VIN = VIL or VIH
		3.0		2.56	2.46	V		±12 mA
		4.5		3.86	3.76		IOH	±24 mA
		5.5		4.86	4.76			±24 mA
VOL	Maximum Low Level	3.0	0.002	0.1	0.1		IOUT = 50 μA
	Output Voltage	4.5	0.001	0.1	0.1	V
		5.5	0.001	0.1	0.1
							*VIN = VIL or VIH
		3.0		0.36	0.44	V		12 mA
		4.5		0.36	0.44		IOL	24 mA
		5.5		0.36	0.44			24 mA
IIN	Maximum Input			±	±	μ
	Leakage Current	5.5		0.1	1.0	A	VI = VCC, GND
IOZ	Maximum			±0.5	±5.0	μA	VI (OE) = VIL, VIH
	3-State	5.5					VI = VCC, GND
	Current						VO = VCC, GND
IOLD	²Minimum Dynamic	5.5			75	mA	VOLD = 1.65 V Max
	Output Current
IOHD		5.5			±75	mA	VOHD = 3.85 V Min
ICC	Maximum Quiescent					μ
	Supply Current	5.5		8.0	80	A	VIN = VCC or GND

* All outputs loaded; thresholds on input associated with output under test. ² Maximum test duration 2.0 ms, one output loaded at a time.

Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.

FACT DATA

5-3