MOTOROLA MC74HC595AN, MC74HC595AFL1, MC74HC595AFL2, MC74HC595AFR1, MC74HC595AFR2 Datasheet

MC74HC595A

8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs

High±Performance Silicon±Gate CMOS

The MC74HC595A consists of an 8±bit shift register and an 8±bit D±type latch with three±state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8±bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register.

The HC595A directly interfaces with the SPI serial data port on CMOS MPUs and MCUs.

•Output Drive Capability: 15 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1.0 μA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 328 FETs or 82 Equivalent Gates

•Improvements over HC595

ÐImproved Propagation Delays

Ð50% Lower Quiescent Power

ÐImproved Input Noise and Latchup Immunity

LOGIC DIAGRAM

SERIAL

DATA A 14

INPUT

SHIFT

REGISTER

SHIFT 11

CLOCK

RESET 10

LATCH 12

CLOCK

OUTPUT 13

ENABLE

	15		QA
	1
			QB
	2
			QC
	3				PARALLEL
			QD
	4				DATA
			QE
					OUTPUTS
LATCH	5
			QF
	6
			QG
	7
			QH

	9 SQ	SERIAL
		DATA
	H
		OUTPUT
	VCC = PIN 16
	GND = PIN 8

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			MARKING
			DIAGRAMS
			16
		PDIP±16	MC74HC595AN
		N SUFFIX
	16		AWLYYWW
		CASE 648
	1		1
			16
		SO±16	HC595A
		D SUFFIX
	16		AWLYWW
		CASE 751B
	1
			1
			16
		TSSOP±16	HC
	16	DT SUFFIX	595A
	1	CASE 948F	ALYW
			1
	A	= Assembly Location
	WL	= Wafer Lot
	YY	= Year

WW = Work Week

PIN ASSIGNMENT

QB		1	16	VCC
QC		2	15	QA
QD		3	14	A
QE		4	13	OUTPUT ENABLE
QF		5	12	LATCH CLOCK
QG		6	11	SHIFT CLOCK
QH		7	10	RESET
GND		8	9	SQH

ORDERING INFORMATION

Device	Package	Shipping
MC74HC595AN	PDIP±16	2000 / Box
MC74HC595AD	SOIC±16	48 / Rail
MC74HC595ADR2	SOIC±16	2500 / Reel
MC74HC595ADT	TSSOP±16	96 / Rail
MC74HC595ADTR2	TSSOP±16	2500 / Reel

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 8		MC74HC595A/D

MC74HC595A

MAXIMUM RATINGS*

	Symbol	Parameter		Value	Unit
	VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
	Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Iin	DC Input Current, per Pin		± 20	mA
	Iout	DC Output Current, per Pin		± 35	mA
	ICC	DC Supply Current, VCC and GND Pins		± 75	mA
	PD	Power Dissipation in Still Air,	Plastic DIP²	750	mW
			SOIC Package²	500
			TSSOP Package²	450
	Tstg	Storage Temperature		± 65 to + 150	_C
	TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
		(Plastic DIP, SOIC or TSSOP Package)		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage		0	VCC	V
	(Referenced to GND)
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time	VCC = 2.0 V	0	1000	ns
	(Figure 1)	VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

					Guaranteed Limit
				VCC
					± 55 to	v _	v	_
Symbol	Parameter	Test Conditions		V	_				Unit
					25 C	85 C		125 C
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V		2.0	1.5	1.5		1.5	V
	Voltage	|Iout| v 20 μA		3.0	2.1	2.1		2.1
				4.5	3.15	3.15		3.15
				6.0	4.2	4.2		4.2
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V		2.0	0.5	0.5		0.5	V
	Voltage	|Iout| v 20 μA		3.0	0.9	0.9		0.9
				4.5	1.35	1.35		1.35
				6.0	1.8	1.8		1.8
VOH	Minimum High±Level Output	Vin = VIH or VIL		2.0	1.9	1.9		1.9	V
	Voltage, QA ± QH	|Iout| v 20 μA		4.5	4.4	4.4		4.4
				6.0	5.9	5.9		5.9
		Vin = VIH or VIL	|Iout| v 2.4 mA	3.0	2.48	2.34		2.2
			|Iout| v 6.0 mA	4.5	3.98	3.84		3.7
			|Iout| v 7.8 mA	6.0	5.48	5.34		5.2
VOL	Maximum Low±Level Output	Vin = VIH or VIL		2.0	0.1	0.1		0.1	V
	Voltage, QA ± QH	|Iout| v 20 μA		4.5	0.1	0.1		0.1
				6.0	0.1	0.1		0.1
		Vin = VIH or VIL	|Iout| v 2.4 mA	3.0	0.26	0.33		0.4
			|Iout| v 6.0 mA	4.5	0.26	0.33		0.4
			|Iout| v 7.8 mA	6.0	0.26	0.33		0.4

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MC74HC595A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

					Guaranteed Limit
				VCC	± 55 to
Symbol	Parameter	Test Conditions		V	25_C	v 85_C	v 125_C	Unit
VOH	Minimum High±Level Output	Vin = VIH or VIL		2.0	1.9	1.9	1.9	V
	Voltage, SQH	IIoutI v 20 μA		4.5	4.4	4.4	4.4
				6.0	5.9	5.9	5.9
		Vin = VIH or VIL	|Iout| v 2.4 mA	3.0	2.98	2.34	2.2
			IIoutI v 4.0 mA	4.5	3.98	3.84	3.7
			IIoutIv 5.2 mA	6.0	5.48	5.34	5.2
VOL	Maximum Low±Level Output	Vin = VIH or VIL		2.0	0.1	0.1	0.1	V
	Voltage, SQH	IIoutI v 20 μA		4.5	0.1	0.1	0.1
				6.0	0.1	0.1	0.1
		Vin = VIH or VIL	|Iout| v 2.4 mA	3.0	0.26	0.33	0.4
			IIoutI v 4.0 mA	4.5	0.26	0.33	0.4
			IIoutIv 5.2 mA	6.0	0.26	0.33	0.4
Iin	Maximum Input Leakage	Vin = VCC or GND		6.0	± 0.1	± 1.0	± 1.0	μA
	Current
IOZ	Maximum Three±State	Output in High±Impedance State		6.0	± 0.5	± 5.0	± 10	μA
	Leakage	Vin = VIL or VIH
	Current, QA ± QH	Vout = VCC or GND
ICC	Maximum Quiescent Supply	Vin = VCC or GND		6.0	4.0	40	160	μA
	Current (per Package)	lout = 0 μA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

			Guaranteed Limit
		VCC
			± 55 to	v _		v	_
Symbol	Parameter	V	_		C			Unit
			25 C	85			125 C
fmax	Maximum Clock Frequency (50% Duty Cycle)	2.0	6.0	4.8			4.0	MHz
	(Figures 1 and 7)	3.0	15	10			8.0
		4.5	30	24			20
		6.0	35	28			24
tPLH,	Maximum Propagation Delay, Shift Clock to SQH	2.0	140	175			210	ns
tPHL	(Figures 1 and 7)	3.0	100	125			150
		4.5	28	35			42
		6.0	24	30			36
tPHL	Maximum Propagation Delay, Reset to SQH	2.0	145	180			220	ns
	(Figures 2 and 7)	3.0	100	125			150
		4.5	29	36			44
		6.0	25	31			38
tPLH,	Maximum Propagation Delay, Latch Clock to QA ± QH	2.0	140	175			210	ns
tPHL	(Figures 3 and 7)	3.0	100	125			150
		4.5	28	35			42
		6.0	24	30			36
tPLZ,	Maximum Propagation Delay, Output Enable to QA ± QH	2.0	150	190			225	ns
tPHZ	(Figures 4 and 8)	3.0	100	125			150
		4.5	30	38			45
		6.0	26	33			38
tPZL,	Maximum Propagation Delay, Output Enable to QA ± QH	2.0	135	170			205	ns
tPZH	(Figures 4 and 8)	3.0	90	110			130
		4.5	27	34			41
		6.0	23	29			35
tTLH,	Maximum Output Transition Time, QA ± QH	2.0	60	75			90	ns
tTHL	(Figures 3 and 7)	3.0	23	27			31
		4.5	12	15			18
		6.0	10	13			15

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MC74HC595A

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

			Guaranteed Limit
		VCC	± 55 to
Symbol	Parameter	V	25_C	v 85_C	v 125_C	Unit
tTLH,	Maximum Output Transition Time, SQH	2.0	75	95	110	ns
tTHL	(Figures 1 and 7)	3.0	27	32	36
		4.5	15	19	22
		6.0	13	16	19
Cin	Maximum Input Capacitance	Ð	10	10	10	pF
Cout	Maximum Three±State Output Capacitance (Output in	Ð	15	15	15	pF
	High±Impedance State), QA ± QH

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Package)*	300	pF

*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

TIMING REQUIREMENTS (Input tr = tf = 6.0 ns)

			Guaranteed Limit
		VCC
			25_C to
Symbol	Parameter	V	± 55_C	v 85_C	v 125_C	Unit
tsu	Minimum Setup Time, Serial Data Input A to Shift Clock	2.0	50	65	75	ns
	(Figure 5)	3.0	40	50	60
		4.5	10	13	15
		6.0	9.0	11	13
tsu	Minimum Setup Time, Shift Clock to Latch Clock	2.0	75	95	110	ns
	(Figure 6)	3.0	60	70	80
		4.5	15	19	22
		6.0	13	16	19
th	Minimum Hold Time, Shift Clock to Serial Data Input A	2.0	5.0	5.0	5.0	ns
	(Figure 5)	3.0	5.0	5.0	5.0
		4.5	5.0	5.0	5.0
		6.0	5.0	5.0	5.0
trec	Minimum Recovery Time, Reset Inactive to Shift Clock	2.0	50	65	75	ns
	(Figure 2)	3.0	40	50	60
		4.5	10	13	15
		6.0	9.0	11	13
tw	Minimum Pulse Width, Reset	2.0	60	75	90	ns
	(Figure 2)	3.0	45	60	70
		4.5	12	15	18
		6.0	10	13	15
tw	Minimum Pulse Width, Shift Clock	2.0	50	65	75	ns
	(Figure 1)	3.0	40	50	60
		4.5	10	13	15
		6.0	9.0	11	13
tw	Minimum Pulse Width, Latch Clock	2.0	50	65	75	ns
	(Figure 6)	3.0	40	50	60
		4.5	10	13	15
		6.0	9.0	11	13
tr, tf	Maximum Input Rise and Fall Times	2.0	1000	1000	1000	ns
	(Figure 1)	3.0	800	800	800
		4.5	500	500	500
		6.0	400	400	400

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