MOTOROLA MC74HCT138AFEL, MC74HCT138AFL1, MC74HCT138AFL2, MC74HCT138ADTR2, MC74HCT138AF Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

1-of-8 Decoder/Demultiplexer MC74HCT138A with LSTTL Compatible Inputs

	High±Performance Silicon±Gate CMOS			N SUFFIX
	16		PLASTIC PACKAGE
	The MC74HCT138A is identical in pinout to the LS138. The HCT138A			CASE 648±08
	may be used as a level converter for interfacing TTL or NMOS outputs to	1
	High Speed CMOS inputs.			D SUFFIX
	The HCT138A decodes a three±bit Address to one±of±eight active±lot
		16	SOIC PACKAGE
	outputs. This device features three Chip Select inputs, two active±low and
				CASE 751B±05
	one active±high to facilitate the demultiplexing, cascading, and chip±select-		1
	ing functions. The demultiplexing function is accomplished by using the			DT SUFFIX
	Address inputs to select the desired device output; one of the Chip Selects is	16
	used as a data input while the other Chip Selects are held in their active		TSSOP PACKAGE
	states.		1	CASE 948F±01
	• Output Drive Capability: 10 LSTTL Loads		ORDERING INFORMATION
	• TTL/NMOS Compatible Input Levels
			MC74HCTXXXAN	Plastic
	• Outputs Directly Interface to CMOS, NMOS, and TTL
			MC74HCTXXXAD	SOIC
	• Operating Voltage Range: 4.5 to 5.5 V
			MC74HCTXXXADT TSSOP

•Low Input Current: 1.0 μA

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

• Chip Complexity: 122 FETs or 30.5 Equivalent Gates

PIN ASSIGNMENT

LOGIC DIAGRAM

A0

1

16

VCC

A1

2

15

Y0

3

14

A0

1

15

Y0

A2

Y1

4

13

ADDRESS

A1

2

14

Y1

CS2

Y2

INPUTS

3

13

CS3

5

12

Y3

A2

Y2

12

Y3

ACTIVE±LOW

CS1

6

11

Y4

Y7

7

10

Y5

11

Y4

OUTPUTS

GND

8

9

Y6

10

Y5

9

Y6

7

Y7

6

FUNCTION TABLE

CHIP±

CS1

Inputs

Outputs

4

PIN 16 = VCC

CS1CS2 CS3

A2 A1 A0

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

SELECT CS2

INPUTS

5

PIN 8 = GND

X

X

H

X

X

X

H

H

H

H

H

H

H

H

CS3

X

H

X

X

X

X

H

H

H

H

H

H

H

H

L X X

X X X

H H H H H H H H

H L L

L L L

L H H H H H H H

Design Criteria

Value

Units

H L L

L L H

H L H H H H H H

H L L

L H L

H H L H H H H H

Internal Gate Count*

30.5

ea.

H L L

L H H

H H H L H H H H

Internal Gate Propagation Delay

1.5

ns

H L L

H L L

H H H H L H H H

H L L

H L H

H H H H H L H

H

Internal Gate Power Dissipation

5.0

μW

H

L

L

H

H

L

H

H

H

H

H

H

L

H

H L L

H H H

H H H H H H H L

Speed Power Product

.0075

pJ

H = high level (steady state)

L = low level (steady state)

*Equivalent to a two±input NAND gate.

X = don't care

10/95

Motorola, Inc. 1995

REV 6

MC74HCT138A

MAXIMUM RATINGS*

Symbol	Parameter		Value	Unit
VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin		± 20	mA
Iout	DC Output Current, per Pin		± 25	mA
ICC	DC Supply Current, VCC and GND Pins		± 50	mA
PD	Power Dissipation in Still Air	Plastic DIP²	750	mW
		SOIC Package²	500
		TSSOP Package²	450
Tstg	Storage Temperature		± 65 to + 150	_C
TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
	(Plastic DIP, TSSOP or SOIC Package)		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter	Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)	4.5	5.5	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)	0	VCC	V
TA	Operating Temperature, All Package Types	± 55	+ 125	_C
tr, tf	Input Rise and Fall Time (Figure 1)	0	500	ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC
				± 55 to	v _		v	_
Symbol	Parameter	Test Conditions	V	_					Unit
				25 C	85 C			125 C
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V	4.5	2.0	2.0			2.0	V
	Voltage	|Iout| v 20 μA	5.5	2.0	2.0			2.0
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V	4.5	0.8	0.8			0.8	V
	Voltage	|Iout| v 20 μA	5.5	0.8	0.8			0.8
VOH	Minimum High±Level Output	Vin = VIH or VIL	4.5	4.4	4.4			4.4	V
	Voltage	|Iout| v 20 μA	5.5	5.4	5.4			5.4
		Vin = VIH or VIL
		|Iout| v 4.0 μA	4.5	3.98	3.84			3.7
VOL	Maximum Low±Level Output	Vin = VIH or VIL	4.5	0.1	0.1			0.1	V
	Voltage	|Iout| v 20 μA	5.5	0.1	0.1			0.1
		Vin = VIH or VIL
		|Iout| v 4.0 mA	4.5	0.26	0.33			0.4
Iin	Maximum Input Leakage Current	Vin = VCC or GND	6.0	± 0.1	± 1.0			± 1.0	μA
ICC	Maximum Quiescent Supply	Vin = VCC or GND	5.5	4.0	40			160	μA
	Current (per Package)	Iout = 0 μA
ICC	Additional Quiescent Supply	Vin = 2.4 V, Any One Input		≥ ± 55_C	25_C to 125_C
	Current	Vin = VCC or GND, Other Inputs
		lout = 0 μA	5.5	2.9		2.4			mA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

MOTOROLA

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