MOTOROLA MC74HC132AN, MC74HC132AFL1, MC74HC132AFL2, MC74HC132AFR1, MC74HC132AFR2 Datasheet

MC74HC132A

Quad 2-Input NAND Gate with Schmitt-Trigger Inputs

High±Performance Silicon±Gate CMOS

The MC74HC132A is identical in pinout to the LS132. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

The HC132A can be used to enhance noise immunity or to square up slowly changing waveforms.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1.0 μA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 72 FETs or 18 Equivalent Gates

LOGIC DIAGRAM

A1 1

3

Y1

2

B1

A2 4

6

Y2

5

B2

Y = AB

A3 9

8

Y3

B3 10

A4 12

11 Y4

B4 13

PIN 14 = VCC

PIN 7 = GND

FUNCTION TABLE

Inputs			Output
A		B	Y
L		L	H
L		H	H
H		L	H
H		H	L

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				MARKING
				DIAGRAMS
				14
		PDIP±14		MC74HC132AN
		N SUFFIX
				AWLYYWW
		CASE 646
				1
				14
		SOIC±14		HC132A
		D SUFFIX
				AWLYWW
	CASE 751A
				1
	A	= Assembly Location
	WL or L = Wafer Lot
	YY or Y	= Year
	WW or W = Work Week
	PIN ASSIGNMENT
	A1	1	14	VCC
	B1	2	13	B4
	Y1	3	12	A4
	A2	4	11	Y4
	B2	5	10	B3
	Y2	6	9	A3
	GND	7	8	Y3

ORDERING INFORMATION

Device	Package	Shipping
MC74HC132AN	PDIP±14	2000 / Box
MC74HC132AD	SOIC±14	55 / Rail
MC74HC132ADR2	SOIC±14	2500 / Reel

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 7		MC74HC132A/D

MC74HC132A

MAXIMUM RATINGS*

Symbol	Parameter		Value	Unit
VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
Vin	DC Input Voltage (Referenced to GND)		± 1.5 to VCC + 1.5	V
Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin		± 20	mA
Iout	DC Output Current, per Pin		± 25	mA
ICC	DC Supply Current, VCC and GND Pins		± 50	mA
PD	Power Dissipation in Still Air,	Plastic DIP²	750	mW
	SOIC Package²		500
Tstg	Storage Temperature		± 65 to + 150	_C
TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
	(Plastic DIP or SOIC Package)		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter	Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)	2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage	0	VCC	V
	(Referenced to GND)
TA	Operating Temperature, All Package Types	± 55	+ 125	_C
tr, tf	Input Rise and Fall Time (Figure 1)	Ð	no	ns
			limit*

*When Vin X 0.5 VCC, ICC >> quiescent current.

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

					Guaranteed Limit
			VCC
						± 40_C to			± 55_C to
Symbol	Parameter	Test Conditions	V	_		+ 85	_	C	+ 125	_	C	Unit
				25 C
VT+ max	Maximum Positive±Going	Vout = 0.1 V	2.0	1.5		1.5			1.5			V
	Input Threshold Voltage	|Iout| v 20 μA	4.5	3.15		3.15			3.15
	(Figure 3)		6.0	4.2		4.2			4.2
VT+ min	Minimum Positive±Going	Vout = 0.1 V	2.0	1.0		0.95			0.95			V
	Input Threshold Voltage	|Iout| v 20 μA	4.5	2.3		2.25			2.25
	(Figure 3)		6.0	3.0		2.95			2.95
VT± max	Maximum Negative±Going	Vout = VCC ± 0.1 V	2.0	0.9		0.95			0.95			V
	Input Threshold Voltage	|Iout| v 20 μA	4.5	2.0		2.05			2.05
	(Figure 3)		6.0	2.6		2.65			2.65
VT± min	Minimum Negative±Going	Vout = VCC ± 0.1 V	2.0	0.3		0.3			0.3			V
	Input Threshold Voltage	|Iout| v 20 μA	4.5	0.9		0.9			0.9
	(Figure 3)		6.0	1.2		1.2			1.2
VHmax	Maximum Hysteresis Voltage	Vout = 0.1 V or VCC ± 0.1 V	2.0	1.2		1.2			1.2			V
Note 2	(Figure 3)	|Iout| v 20 μA	4.5	2.25		2.25			2.25
			6.0	3.0		3.0			3.0
VHmin	Minimum Hysteresis Voltage	Vout = 0.1 V or VCC ± 0.1 V	2.0	0.2		0.2			0.2			V
Note 2	(Figure 3)	|Iout| v 20 μA	4.5	0.4		0.4			0.4
			6.0	0.5		0.5			0.5

NOTE: 1. VHmin > (VT+ min) ± (VT± max); VHmax = (VT+ max) + (VT± min).

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

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MC74HC132A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

					Guaranteed Limit
				VCC
					± 55 to
Symbol	Parameter	Test Conditions		V	25_C	v 85_C	v 125_C	Unit
VOH	Minimum High±Level Output	VinvVT± min or VT+ max		2.0	1.9	1.9	1.9	V
	Voltage	|Iout| v 20 μA		4.5	4.4	4.4	4.4
				6.0	5.9	5.9	5.9
		Vinv±VT± min or VT+ max		4.5	3.98	3.84	3.7
			|Iout| v 4.0 mA
			|Iout| v 5.2 mA	6.0	5.48	5.34	5.2
VOL	Maximum Low±Level Output	Vin ≥ VT+ max		2.0	0.1	0.1	0.1	V
	Voltage	|Iout| v 20 μA		4.5	0.1	0.1	0.1
				6.0	0.1	0.1	0.1
		Vin≥ VT+ max	|Iout| v 4.0 mA	4.5	0.26	0.33	0.4
			|Iout| v 5.2 mA	6.0	0.26	0.33	0.4
Iin	Maximum Input Leakage	Vin = VCC or GND		6.0	± 0.1	± 1.0	± 1.0	μA
	Current
ICC	Maximum Quiescent Supply	Vin = VCC or GND		6.0	1.0	10	40	μA
	Current (per Package)	Iout = 0 μA

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

			Guaranteed Limit
		VCC
			± 55 to
Symbol	Parameter	V	25_C	v 85_C	v 125_C	Unit
tPLH,	Maximum Propagation Delay, Input A or B to Output Y	2.0	125	155	190	ns
tPHL	(Figures 1 and 2)	4.5	25	31	38
		6.0	21	26	32
tTLH,	Maximum Output Transition Time, Any Output	2.0	75	95	110	ns
tTHL	(Figures 1 and 2)	4.5	15	19	22
		6.0	13	16	19
Cin	Maximum Input Capacitance	Ð	10	10	10	pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Gate)*	24	pF

*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

	tr	tf	VCC		TEST POINT
INPUT	90%
	50%				OUTPUT
A OR B	10%		GND
				DEVICE
	tPHL	tPLH
				UNDER
	90%				CL*
Y				TEST
	50%
	10%
	tTHL		tTLH
				*Includes all probe and jig capacitance
	Figure 1. Switching Waveforms			Figure 2. Test Circuit

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