MOTOROLA MC74HC240AFL2, MC74HC240AFR1, MC74HC240AFR2, MC74HC240AFEL, MC74HC240ADWR2 Datasheet

MC74HC240A

Octal 3-State Inverting

Buffer/Line Driver/Line

Receiver

High±Performance Silicon±Gate CMOS

The MC74HC240A is identical in pinout to the LS240. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This octal noninverting buffer/line driver/line receiver is designed to be used with 3±state memory address drivers, clock drivers, and other sub±oriented systems. The device has inverting outputs and two active±low output enables.

The HC240A is similar in function to the HC244A.

•Output Drive Capability: 15 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2 to 6 V

•Low Input Current: 1 μA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 120 FETs or 30 Equivalent Gates

LOGIC DIAGRAM

	A1	2			18	YA1
	A2	4			16	YA2
	A3	6			14	YA3
	A4	8			12	YA4
DATA						INVERTING
INPUTS	B1	11			9	OUTPUTS
						YB1
	B2	13			7	YB2
	B3	15			5	YB3
	B4	17			3	YB4
			1		PIN 20 = VCC
OUTPUT	ENABLE A				PIN 10 = GND
ENABLES	ENABLE B		19
			FUNCTION TABLE
			Inputs		Outputs
			Enable A,
			Enable B	A, B	YA, YB
			L	L	H
			L	H	L
			H	X	Z

Z = high impedance

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			MARKING
		DIAGRAMS
		20
	PDIP±20	MC74HC240AN
	N SUFFIX
			AWLYYWW
20	CASE 738
1		1
		20
	SOIC WIDE±20		HC240A
20	DW SUFFIX
			AWLYYWW
1	CASE 751D
		1	20
	TSSOP±20		HC
20	DT SUFFIX		240A
1	CASE 948E		ALYW
			1

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

PIN ASSIGNMENT

ENABLE A	1	20	VCC
A1	2	19	ENABLE B
YB4	3	18	YA1
A2	4	17	B4
YB3	5	16	YA2
A3	6	15	B3
YB2	7	14	YA3
A4	8	13	B2
YB1	9	12	YA4
GND	10	11	B1

ORDERING INFORMATION

Device	Package	Shipping
MC74HC240AN	PDIP±20	1440 / Box
MC74HC240ADW	SOIC±WIDE	38 / Rail
MC74HC240ADWR2	SOIC±WIDE	1000 / Reel
MC74HC240ADT	TSSOP±20	75 / Rail
MC74HC240ADTR2	TSSOP±20	2500 / Reel

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
May, 2000 ± Rev. 9		MC74HC240A/D

MC74HC240A

MAXIMUM RATINGS*

Symbol	Parameter		Value	Unit
VCC	DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
Vin	DC Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Vout	DC Output Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin		± 20	mA
Iout	DC Output Current, per Pin		± 35	mA
ICC	DC Supply Current, VCC and GND Pins		± 75	mA
PD	Power Dissipation in Still Air,	Plastic DIP²	750	mW
		SOIC Package²	500
		TSSOP Package²	450
Tstg	Storage Temperature		± 65 to + 150	_C
TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
	(Plastic DIP, SOIC or TSSOP Package)		260

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C

TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)		0	VCC	V
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time	VCC = 2.0 V	0	1000	ns
	(Figure 1)	VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

					Guaranteed Limit
				VCC	± 55 to
Symbol	Parameter	Test Conditions		V	25_C	v 85_C	v 125_C	Unit
VIH	Minimum High±Level Input	Vout = VCC ± 0.1 V		2.0	1.5	1.5	1.5	V
	Voltage	|Iout| v 20	μA	3.0	2.1	2.1	2.1
				4.5	3.15	3.15	3.15
				6.0	4.2	4.2	4.2
VIL	Maximum Low±Level Input	Vout = 0.1 V		2.0	0.5	0.5	0.5	V
	Voltage	|Iout| v 20 μA		3.0	0.9	0.9	0.9
				4.5	1.35	1.35	1.35
				6.0	1.8	1.8	1.8
VOH	Minimum High±Level Output	Vin = VIH	μA	2.0	1.9	1.9	1.9	V
	Voltage	|Iout| v 20		4.5	4.4	4.4	4.4
				6.0	5.9	5.9	5.9
		Vin = VIH	|Iout| v 2.4 mA	3.0	2.48	2.34	2.2
			|Iout| v 6.0 mA	4.5	3.98	3.84	3.7
			|Iout| v 7.8 mA	6.0	5.48	5.34	5.2
VOL	Maximum Low±Level Output	Vin = VIL	μA	2.0	0.1	0.1	0.1	V
	Voltage	|Iout| v 20		4.5	0.1	0.1	0.1
				6.0	0.1	0.1	0.1
		Vin = VIL	|Iout| v 2.4 mA	3.0	0.26	0.33	0.4
			|Iout| v 6.0 mA	4.5	0.26	0.33	0.4
			|Iout| v 7.8 mA	6.0	0.26	0.33	0.4

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MC74HC240A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC	± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit
Iin	Maximum Input Leakage	Vin = VCC or GND	6.0	± 0.1	± 1.0	± 1.0	μA
	Current
IOZ	Maximum Three±State	Output in High±Impedance State	6.0	± 0.5	± 5.0	± 10	μA
	Leakage Current	Vin = VIL or VIH
		Vout = VCC or GND
ICC	Maximum Quiescent Supply	Vin = VCC or GND	6.0	4.0	40	160	μA
	Current (per Package)	Iout = 0 μA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

			Guaranteed Limit
		VCC
			± 55 to
Symbol	Parameter	V	25_C	v 85_C	v 125_C	Unit
tPLH,	Maximum Propagation Delay, A to YA or B to YB	2.0	80	100	120	ns
tPHL	(Figures 1 and 3)	3.0	40	50	60
		4.5	16	20	24
		6.0	14	17	20
tPLZ,	Maximum Propagation Delay, Output Enable to YA or YB	2.0	110	140	165	ns
tPHZ	(Figures 2 and 4)	3.0	60	70	80
		4.5	22	28	33
		6.0	19	24	28
tPZL,	Maximum Propagation Delay, Output Enable to YA or YB	2.0	110	140	165	ns
tPZH	(Figures 2 and 4)	3.0	60	70	80
		4.5	22	28	33
		6.0	19	24	28
tTLH,	Maximum Output Transition Time, Any Output	2.0	60	75	90	ns
tTHL	(Figures 1 and 3)	3.0	23	27	32
		4.5	12	15	18
		6.0	10	13	15
Cin	Maximum Input Capacitance	Ð	10	10	10	pF
Cout	Maximum Three±State Output Capacitance (Output in	Ð	15	15	15	pF
	High±Impedance State)

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Transceiver Channel)*	32	pF

*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the ON Semiconductor High±Speed CMOS Data Book (DL129/D).

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